A Single-Trim frequency reference system with 0.7 ppm/°C from −63 °C to 165 °C Consuming 210 μW at 70 MHz

This article presents a frequency reference system that combines high frequency accuracy and low power consumption using a single-point temperature trim and batch calibration. The system is intended as a low-cost fully integrated crystal oscillator replacement. In this system, the oscillation frequency of a power-efficient, but process, voltage, temperature (PVT) and lifetime (L)-sensitive current-controlled ring oscillator (CCO) is periodically (re)calibrated by the well-behaved frequency stability of an untuned LC -based Colpitts oscillator (LCO), which is optimized for stability over PVT variations and lifetime (PVTL). During the single-point room temperature factory trim, the frequency of the LCO is determined and the result is digitally stored. An on-chip calibration engine tunes the CCO to the target frequency based on the LCO frequency, temperature sensor information, and digitally stored trimming information, thus effectively improving the frequency stability of the ring oscillator. The relatively high-power LCO is heavily duty-cycled to minimize the overall power consumption. A prototype fabricated in a 0.13- μ m high-voltage (HV) CMOS SOI process and assembled in a plastic package demonstrates an inaccuracy lower than ±93 ppm over a temperature range from -63 °C to 165 °C across 18 samples. The presented frequency reference system, including on-chip voltage regulators and a temperature sensor, occupies a chip area of 0.69 mm2 and consumes about 64 μA from a single 3.3-V supply. The frequency error due to supply variation is roughly 92 ppm/V. The mean frequency shift due to aging, measured before and after a six-day storage bake at 175 °C, is only 52 ppm.</p

Design of a Digital Temperature Sensor based on Thermal Diffusivity in a Nanoscale CMOS Technology

Temperature sensors are widely used in microprocessors to monitor on-chip temperature gradients and hot-spots, which are known to negatively impact reliability. Such sensors should be small to facilitate floor planning, fast to track millisecond thermal transients, and easy to trim to reduce the associated costs. Recently, it has been shown that thermal diffusivity (TD) sensors can meet these requirements. These sensors operate by digitalizing the temperature-dependent delay associated with the diffusion of heat pulses through an electro-thermal filter (ETF), which, in standard CMOS, can be readily implemented as a resistive heater surrounded by a thermopile. Unlike BJT-based temperature sensors, their accuracy actually improves with CMOS scaling, since it is mainly limited by the accuracy of the heather/thermopile spacing. In this work is presented the electrical design of an highly digital TD sensor in 0.13 µm CMOS with an accuracy better than 1 ºC resolution at with 1 kS/s sampling rate, and which compares favourably to state-of-the-art sensors with similar accuracy and sampling rates [1][2][3][4]. This advance is mainly enabled by the adoption of a highly digital CCO-based phasedomain ΔΣ ADC. The TD sensor presented consists of an ETF, a transconductance stage, a current-controlled oscillator (CCO) and a 6 bit digital counter. In order to be easily ported to nanoscale CMOS technologies, it is proposed to use a sigmadelta modulator based on a CCO as an alternative to traditional modulators. And since 70% of the sensor’s area is occupied by digital circuitry, porting the sensor to latest CMOS technologies process should reduce substantially the occupied die area, and thus reduce significantly the total sensor area

Digital controlled oscillator (DCO) for all digital phase-locked loop (ADPLL) – a review

Digital controlled oscillator (DCO) is becoming an attractive replacement over the voltage control oscillator (VCO) with the advances of digital intensive research on all-digital phase locked-loop (ADPLL) in complementary metal-oxide semiconductor (CMOS) process technology. This paper presents a review of various CMOS DCO schemes implemented in ADPLL and relationship between the DCO parameters with ADPLL performance. The DCO architecture evaluated through its power consumption, speed, chip area, frequency range, supply voltage, portability and resolution. It can be concluded that even though there are various schemes of DCO that have been implemented for ADPLL, the selection of the DCO is frequently based on the ADPLL applications and the complexity of the scheme. The demand for the low power dissipation and high resolution DCO in CMOS technology shall remain a challenging and active area of research for years to come. Thus, this review shall work as a guideline for the researchers who wish to work on all digital PLL

Current-mode processing based Temperature-to-Digital Converters for MEMS applications

This thesis presents novel Temperature-to-Digital Converters (TDCs) designed and fabricated in CMOS technology. These integrated smart temperature sensing circuits are widely employed in the Micro-Electro-Mechanical Systems (MEMS) field in order to mitigate the impact of the ambient temperature on their performance. In this framework, the increasingly stringent demands of the market have led the cost-effectiveness specification of these compensation solutions to an higher and higher level, directly translating into the requirement of more and more compact designs (< 0.1 mm²); in addition to this, considering that the great majority of the systems whose thermal drift needs to be compensated is battery supplied, ultra-low energy-per-conversion (< 10 nJ) is another requirement of primary importance. This thesis provides a detailed description of two different test-chips (mas fuerte and es posible) that have been designed with this orientation and that are the result of three years of research activity; for both devices, the conception, design, layout and testing phases are all described in detail and are supported by simulation and measurement results.This thesis presents novel Temperature-to-Digital Converters (TDCs) designed and fabricated in CMOS technology. These integrated smart temperature sensing circuits are widely employed in the Micro-Electro-Mechanical Systems (MEMS) field in order to mitigate the impact of the ambient temperature on their performance. In this framework, the increasingly stringent demands of the market have led the cost-effectiveness specification of these compensation solutions to an higher and higher level, directly translating into the requirement of more and more compact designs (< 0.1 mm²); in addition to this, considering that the great majority of the systems whose thermal drift needs to be compensated is battery supplied, ultra-low energy-per-conversion (< 10 nJ) is another requirement of primary importance. This thesis provides a detailed description of two different test-chips (mas fuerte and es posible) that have been designed with this orientation and that are the result of three years of research activity; for both devices, the conception, design, layout and testing phases are all described in detail and are supported by simulation and measurement results

Germanium MOSFETs with high-K gate dielectric and advanced source/drain structure

Ph.DDOCTOR OF PHILOSOPH

Ultra-thin plasma nitrided oxide gate dielectrics for advanced MOS transistors

Ultra-thin plasma nitrided oxides have been optimized with the objective to decrease JG and maximize carrier mobility. It was found that while the base oxide cannot be aggressively scaled, plasma optimization yields better mobility thereby increase transistor performance. A summary of the EOT versus gate leakage current density of NMOS devices with plasma nitrided oxides is shown in Figure 5.19. EOT down to 1.2 nm has been achieved with a gate leakage current density of 40 A/cm2 at 1 V operating voltage

Germanium MOS devices integrating high-k dielectric and metal gate

textThis dissertation investigates the fabrication and characteristics of the metaloxide-semiconductor (MOS) devices built on germanium substrates integrating HfO2 high-κ dielectric and TaN metal gate electrode. The metal-gate/high-κ/germanium MOS stack, by taking the advantages of the high carrier mobility from the germanium channel and the sub-nm equivalent-oxide-thickness (EOT) scaling capability from the high-κ dielectric and the metal gate electrode, offers a possible solution for the future advanced complementary MOS (CMOS) applications to further boast the transistors’ driving current for faster operation. Due to the unstable and poor-quality natively grown germanium oxide, surface treatment is very critical in germanium device fabrication in order to remove the native oxide and prevent its growth, as well as suppress the interdiffusion across the interface. Several wet cleaning methods and an in situ cleaning technique by Ar anneal have been investigated. Surface passivation techniques, including NH3-based surface nitridation (SN) by forming a GeOxNy layer and silicon interlayer (SiIL) passivation by growing an ultra-thin (several monolayer) silicon layer between the high-κ dielectric and the substrate, have been studied and proved able to improve device performance significantly. Both p- and n-channel germanium transistors have been successfully fabricated. 1.8X enhancement of peak mobility in p-channel and 2.5X in n-channel over the silicon control devices have been achieved. The interface growth mechanism between the germanium substrate and the dielectric layer has been investigated. Two competing processes occurring at the interface determine the formation of the interfacial layer and affect Ge outdiffusion. Substrate dopants are found playing important roles, which causes the variations in the interfacial layer formation on different types of substrates and so on in the electrical properties. The relatively high diffusivity of dopants and germanium atoms in bulk germanium and the induced structural defects near the surface may severely degrade the device performance. This can well explain the very poor performance of the n-channel devices reported recently by several groups. Performance degradation of the germanium devices after thermal anneal, which is resulting from the interdiffusion and germanium oxide desorption, suggests that thermal stability is a concern in high temperature processes and more stable passivation techniques may be required. Long term reliability study indicates that HfO2 dielectric with SN treatment on germanium is robust against TDDB stress and the long term reliability (TDDB) is not a concern for germanium MOS devices.Electrical and Computer Engineerin

Micromachines for Dielectrophoresis

An outstanding compilation that reflects the state-of-the art on Dielectrophoresis (DEP) in 2020. Contributions include: - A novel mathematical framework to analyze particle dynamics inside a circular arc microchannel using computational modeling. - A fundamental study of the passive focusing of particles in ratchet microchannels using direct-current DEP. - A novel molecular version of the Clausius-Mossotti factor that bridges the gap between theory and experiments in DEP of proteins. - The use of titanium electrodes to rapidly enrich T. brucei parasites towards a diagnostic assay. - Leveraging induced-charge electrophoresis (ICEP) to control the direction and speed of Janus particles. - An integrated device for the isolation, retrieval, and off-chip recovery of single cells. - Feasibility of using well-established CMOS processes to fabricate DEP devices. - The use of an exponential function to drive electrowetting displays to reduce flicker and improve the static display performance. - A novel waveform to drive electrophoretic displays with improved display quality and reduced flicker intensity. - Review of how combining electrode structures, single or multiple field magnitudes and/or frequencies, as well as variations in the media suspending the particles can improve the sensitivity of DEP-based particle separations. - Improvement of dielectrophoretic particle chromatography (DPC) of latex particles by exploiting differences in both their DEP mobility and their crossover frequencies