A RISC-V based medical implantable SOC for high voltage a current tissue stimulus

A RISC-V based System on Chip (SoC) for high voltage and current tissue stimulus, targeting implantable medical devices, is presented. The circuit is designed in a 0.18μm HV-CMOS process, including the RISC-V 32RVI based microcontroller core, called Siwa —which includes SPI, UART and GPIO interfaces, a packet-based bus and memory controller, and 8kB SRAM—, combined with several biological tissue stimulus and sensing circuits. The complete test chip (analog+RISC-V) occupies a 5mm2 area but only 0.82mm2 correspond to the RISCV micro-controller, which operates up to 20MHz, with average energy needs of less than 48 pJ/cycle (3pJ STD), and for which several reliability and safety issues were considered.Agencia Nacional de Investigación e Innovació

Siwa: A custom RISC-V based system on chip (SOC) for low power medical applications

This work introduces the development of Siwa, a RISC-V RV32I 32-bit based core, intended as a flexible control platform for highly integrated implantable biomedical applications, and implemented on a commercial 0.18 m high voltage (HV) CMOS technology. Simulations show that Siwa can outperform commercial micro-controllers commonly used in the medical industry as control units for implantable devices, with energy requirements below the 50 pJ per clock cycle.Agencia Nacional de Investigación e Innovació

An affordable post-silicon testing framework applied to a RISC-V based microcontroller

The RISC-V architecture is a very attractive option for developing application specific systems needing an affordable yet efficient central processing unit. Post-silicon validation on RISC-V applications has been done in industry for a while, however documentation is scarce. This paper proposes a practical low-cost post-silicon testing framework applied to a RISC-V RV32I based microcontroller. The framework uses FPGA-based emulation as a cornerstone to test the microcontroller before and after its fabrication. The platform only requires a handful of elements like the FPGA, a PC, the fabricated chip and some discrete components, without losing the capacity to functionally validate the design under test and save development testing time by using a re-utilize philosophy.Agencia Nacional de Investigación e Innovació

Optimized Biosignals Processing Algorithms for New Designs of Human Machine Interfaces on Parallel Ultra-Low Power Architectures

The aim of this dissertation is to explore Human Machine Interfaces (HMIs) in a variety of biomedical scenarios. The research addresses typical challenges in wearable and implantable devices for diagnostic, monitoring, and prosthetic purposes, suggesting a methodology for tailoring such applications to cutting edge embedded architectures. The main challenge is the enhancement of high-level applications, also introducing Machine Learning (ML) algorithms, using parallel programming and specialized hardware to improve the performance. The majority of these algorithms are computationally intensive, posing significant challenges for the deployment on embedded devices, which have several limitations in term of memory size, maximum operative frequency, and battery duration. The proposed solutions take advantage of a Parallel Ultra-Low Power (PULP) architecture, enhancing the elaboration on specific target architectures, heavily optimizing the execution, exploiting software and hardware resources. The thesis starts by describing a methodology that can be considered a guideline to efficiently implement algorithms on embedded architectures. This is followed by several case studies in the biomedical field, starting with the analysis of a Hand Gesture Recognition, based on the Hyperdimensional Computing algorithm, which allows performing a fast on-chip re-training, and a comparison with the state-of-the-art Support Vector Machine (SVM); then a Brain Machine Interface (BCI) to detect the respond of the brain to a visual stimulus follows in the manuscript. Furthermore, a seizure detection application is also presented, exploring different solutions for the dimensionality reduction of the input signals. The last part is dedicated to an exploration of typical modules for the development of optimized ECG-based applications

Fault-Tolerant Circuits and Interconnects for Biomedical Implantable Devices

Proyecto de Investigación (Código 1360014) Instituto Tecnológico de Costa Rica. Vicerrectoría de Investigación y Extensión (VIE). Escuela de Ingeniería Electrónica, 2020Los dispositivos médicos implantables (IMDs) son sistemas críticos para la seguridad con requerimientos de potencia muy bajos, los cuales se utilizan para el tratamiento a largo plazo de diferentes condiciones médicas. IMDs utilizan un número de componentes cada vez más elevado (sensores, actuadores, procesadores, bloques de memoria), que tienen que comunicarse entre ellos en un Sistema en Chip (SoC). En este proyecto, diferentes tipos de interconexiones (punto a punto, bus, red en chip) fueron evaluadas considerando su tolerancia a fallas, consumo de potencia y capacidades de comunicación. Como parte de los productos se desarrolló una base de datos escalable sobre sistemas médicos implantables reportados en la literatura hasta el año 2018, con el fin de conocer el estado del arte y las tendencias sobre la incorporación de sistemas electrónicos en este tipo de solución. Basado en este estudio inicial, se procedió a proponer un marco de trabajo de evaluación de interconexiones, el que incorpora un generador de topologías y el flujo de diseño para evaluar estas topologías en términos de potencia y tolerancia a fallas a nivel de simulación, junto con la propuesta de una métrica para comparar diferentes arquitecturas a nivel de pre-síntesis (previo a la consolidación del diseño). Por último, un diseño e implementación a nivel de circuito integrado (IC) de una solución de interconexiones ajustada a IMDs se incorporó en el diseño de un microprocesador a la medida. Este proyecto se desarrolló en el marco de la cooperación con el Centro Médico Erasmus (Erasmus MC) en los Países Bajos y la Universidad Católica del Uruguay

Watchdog Monitoring for Detecting and Handling of Control Flow Hijack on RISC-V-based Binaries

Abstract—Control flow hijacking has been a major challenge in software security. Several means of protections have been developed but insecurities persist. This is because existing protections have sometimes been circumvented while some resilient protections do not cover all applications. Studies have revealed that a holistic way of tackling software insecurity could involve watchdog monitoring and detection via Control Flow Integrity (CFI). The CFI concept has shown a good measure of reliability to mitigate control flow hijacking. However, sophisticated attack techniques in the form of Return Oriented Programming (ROP) have persisted. A flexible protection is desirable, which not only covers as many architecture structures as possible but also mitigates known resilient attacks like ROP. The solution proffered here is a hybrid of CFI and watchdog timing via inter-process signaling (IP-CFI). It is a software-based protection that involves recompilation of the target program. The implementation here is on vulnerable RISC-V-based process but is flexible and could be adapted on other architectures. We present a proof of concept in IP-CFI which when applied to a vulnerable program, ROP is mitigated. The target program incurs a run-time overhead of 1.5%. The code is available

Aspects of Pacemakers

Outstanding steps forward were made in the last decades in terms of identification of endogenous pacemakers and the exploration of their controllability. New "artifical" devices were developed and are now able to do much more than solely pacemaking of the heart. In this book different aspects of pacemaker - functions and interactions, in various organ systems were examined. In addition, various areas of application and the potential side effects and complications of the devices were discussed

An Energy Efficient non-volatile FPGA Digital Processor for Brain Neuromodulation

PhD ThesisBrain stimulation technologies have the potential to provide considerable clinical benefits for people with a range of neurological disorders. Recent neuroscience studies have shown that considerable information of brain states is contained in the low frequency local field potential (If-LFP; below 5Hz) recordings with application in real-time closed-loop neurostimulation for treating neurological disorders. Given these signals can be sampled at low sampling rate and hence provide sparse data streams, there is an opportunity to design implantable neuroprosthesis with long battery lifecycles which enables enough processing power to implement long-term, real-time closed loop control algorithms. In this thesis, a closed-loop embedded digital processor has been created for use in rodent neuroscience experiments. The first contribution of this work is to develop a mathematical analytical design approach of feedback controller for suppressing high-amplitude epileptic activity in the neuron mass model to form a better understanding of how to perform a better closed-loop stimulation to control seizures. The second contribution and the third contribution are combined to present an exploratory energy-efficient digital processor architecture built with commercial off-the-shelf non-volatile FPGAs and microcontroller for sparse data processing of brain neuromodulation. A digital hardware design of an exemplar PID control algorithm has been implemented on this proposed digital architecture. A new power computing diagram of this time-driven approach significantly reduced the power consumption which suggests that a digital combined control system of non-volatile FPGAs and microcontroller outweighs a digital control system of microcontroller with microcontroller regarding computing time cost and energy consumption supposing one microcontroller is always required. Taken together, this digital energy-efficient processor architecture gives important insights and viewpoints for the further advancements of neuroprosthesis for brain neurostimulation to achieve lower power consumption for sparse sampling data rate

Current Issues and Recent Advances in Pacemaker Therapy

Patients with implanted pacemakers or defibrillators are frequently encountered in various healthcare settings. As these devices may be responsible for, or contribute to a variety of clinically significant issues, familiarity with their function and potential complications facilitates patient management. This book reviews several clinically relevant issues and recent advances of pacemaker therapy: implantation, device follow-up and management of complications. Innovations and research on the frontiers of this technology are also discussed as they may have wider utilization in the future. The book should provide useful information for clinicians involved in the management of patients with implanted antiarrhythmia devices and researchers working in the field of cardiac implants

Energy-Efficient PRBS Impedance Spectroscopy on a Digital Versatile Platform

partially_open6siThis research has been partially funded by the Italian Ministry of University and Research (MUR) through the program “Dipartimenti di Eccellenza” (2018-2022). The research has also received partial support from the Italian Ministry of University and Research (MUR) and the Eranet FLAG ERA initiative within CONVERGENCE project (CUP B84I16000030005) through the IUNET Consortium.This paper presents the digital design of a versatile and low-power broadband impedance spectroscopy (IS) system based on pseudo-random binary sequence (PRBS) excitation. The PRBS technique allows fast, and low-power estimation of the impedance spectrum over a wide bandwidth with adequate accuracy, proving to be a good candidate for portable medical devices, especially. This paper covers the low-power design of the firmware algorithms and implements them on a versatile and reconfigurable digital platform that can be easily adjusted to the specific application. It will analyze the digital platform with the aim of reducing power consumption while maintaining adequate accuracy of the estimated spectrum. The paper studies two main algorithms (time-domain and frequency-domain) used for PRBS-based IS and implements both of them on the ultra-low-power GAP-8 digital platform. They are compared in terms of accuracy, measurement time, and power budget, while general design trade-offs are drawn out. The time-domain algorithm demonstrated the best accuracy while the frequency-domain one contributes more to save power and energy. However, analysis of the energy-per-error FOM revealed that the time-domain algorithm outperforms the frequency-domain algorithm offering better accuracy for the same energy consumption. Numerical methods and microprocessor resources are exploited to optimize the implementation of both algorithms achieving 27 ms in processing time, power consumption as low as 1.4 mW and a minimum energy consumption per measurement of 0.5 mJ, for a dense impedance spectrum estimation of 214 points.embargoed_20210525Luciani G.; Crescentini M.; Romani A.; Chiani M.; Benini L.; Tartagni M.Luciani G.; Crescentini M.; Romani A.; Chiani M.; Benini L.; Tartagni M