SELF REFERENCED EDGE DETECTION FOR CMOS PWM TRANSCEIVER

Technique is used to implement the CMOS PWM Transceiver circuit is presented. In this paper, A Self Referenced Edge Detection technique is implemented to analyze a CMOS PWM Transceiver circuit, by comparing the rising edge that is self-delayed by about 0.5 T and the modulated falling edge in one carrier clock cycle. An Area-efficient and high robustness (against timing fluctuations) edge detection enabling PWM communication is achieved without requiring elaborate phase-locked loops. Self-referenced edge detection circuit has the capability of timing error measurement while changing the length of self delay element, adaptive data-rate optimization and delay-line calibration are realized. The measured results with a 65-nm CMOS prototype demonstrate a 2-bit PWM communication, high data rate (4Gbps), small peak to peak jitter(4.8ns), and high reliability (BER > 10−12) with small area occupation (540 μm2) and with high RMS (1.3). For reliability improvement, error check and correction associated with intercycle edge detection is introduced and its effectiveness is verified by 2-bit PWM measurement

A New Multi-Rate Clock and Data Recovery Circuit

A new bit rate adaptive clock and data recovery circuit able to operate in a range from 3.125 Mb/s to 2.5 Gb/s is presented in this work. It is designed in a standard CMOS technology, fed with a single supply voltage of 1.8 V and has a maximum power consumption of 140 mW

Simulación de modulación por ancho de pulso usando Tinkercard

Este trabajo tiene como finalidad usar la plataforma Tinkercard para comprender los conceptos de la señal PWM (modulación por ancho de pulso). Dicha plataforma nos permite crear una simulación don se pueda observar fácilmente términos como el DutyCycle (ciclo de trabajo), el periodo de la señal, la frecuencia de la señal, el tiempo de encendido de la señal, el tiempo de apagado de la señal, entro otras terminologías que se deben tener en cuenta al hacer uso de esta modulación por ancho de pulso. La ventaja más importante del uso de tinkercard es su facilidad de uso y su accesibilidad ya que es gratuita y muy intuitiva, así cualquier persona puede usarla sin previo conocimiento sobre ella

Simulation of pulse width modulation using Tinkercard

Este trabajo tiene como finalidad usar la plata-forma Tinkercard para comprender los conceptos de la señal PWM (modulación por ancho de pulso). Dicha plataforma nos permite crear una simulación don se pueda observar fácil-mente términos como el DutyCycle (ciclo de trabajo), el periodo de la señal, la frecuencia de la señal, el tiempo de encendido de la señal, el tiempo de apagado de la señal, entro otras ter-minologías que se deben tener en cuenta al hacer uso de esta modulación por ancho de pulso. La ventaja más importante del uso de tinkercard es su facilidad de uso y su accesibilidad ya que es gratuita y muy intuitiva, así cualquier persona puede usarla sin previo conocimiento sobre ella

Design of Energy-Efficient Equalization and Data Encoding/Decoding Techniques for Wireline Communication Systems

Ever increasing global internet data traffic has driven up the demand for cutting-edge high-speed wireline communication systems including SerDes PHY for various interfaces, interconnects, data centers servers and switches in optical systems. Operating wireline communications at higher data rates leads to signals suffering from greater channel loss and exponential increase in power consumption, mainly caused by a heavier amount of required equalization. In this dissertation, two distinct methodologies for designing SerDes transceivers are presented: 1) a pulse width modulated (PWM) time-domain feed forward equalizer (FFE) and linearity improvement technique for higher-order pulse amplitude modulation (PAM) including PAM-8, and 2) an inter-symbol interference (ISI)-resilient data encoding and decoding technique with Dicode encoding and error correction logic for low-bandwidth wireline channels, as an alternative strategy for communicating in an energy-efficient way on bandwidth-limited wireline channels without using conventional equalizers or filters. The first topic is a PAM-8 wireline transceiver with receiver-side pulse-width-modulated (PWM) or time-domain based feed forward equalization (FFE) technique. The receiver converts voltage-modulated signals or PAM signals to PWM signals and processes them using inverter based delay elements having rail to rail voltage swing. Time-to-voltage and voltage-to-time converters are designed to have non-linearity with opposite signs with the aim of achieving higher front-end linearity on the receiver. The proposed PAM-8 transceiver can operate from 12.0 Gb/s to 39.6 Gb/s and compensates 14 dB loss at 6.6 GHz with an efficiency of 8.66 pJ/bit in 65 nm CMOS. The second topic is an alternative strategy for communicating on bandwidth-limited wireline channels without using conventional equalizers or filters (FFE, DFE, and CTLE): Inter-symbol interference (ISI) resilient Dicode encoding and error correction for low-bandwidth wireline channels. The key observation is that Dicode-encoded data have no consecutive 1s or -1s. With this known information, the error correction logic at the receiver can correct multi-bit errors due to ISI. Implemented in 65 nm CMOS, the proposed digital encoding and decoding approach can achieve BER less than 10−12 while communicating on a channel with an insertion loss of 24.2 dB and 21.4 dB with 2.56 pJ/bit and 2.66 pJ/bit efficiency while operating at 13.6 Gb/s and 16 Gb/s, respectively

Upgrading the Power Grid Functionalities with Broadband Power Line Communications: Basis, Applications, Current Trends and Challenges

This article reviews the basis and the main aspects of the recent evolution of Broadband Power Line Communications (BB-PLC or, more commonly, BPL) technologies. The article starts describing the organizations and alliances involved in the development and evolution of BPL systems, as well as the standardization institutions working on PLC technologies. Then, a short description of the technical foundation of the recent proposed technologies and a comparison of the main specifications are presented; the regulatory activities related to the limits of emissions and immunity are also addressed. Finally, some representative applications of BPL and some selected use cases enabled by these technologies are summarized, together with the main challenges to be faced.This work was financially supported in part by the Basque Government under the grants IT1426-22, PRE_2021_1_0006, and PRE_2021_1_0051, and by the Spanish Government under the grants PID2021-124706OB-I00 and RTI2018-099162-B-I00 (MCIU/AEI/FEDER, UE, funded by MCIN/AEI/10.13039/501100011033 and by “ERDF A way of making Europe”)

Research and design of high-speed advanced analogue front-ends for fibre-optic transmission systems

In the last decade, we have witnessed the emergence of large, warehouse-scale data centres which have enabled new internet-based software applications such as cloud computing, search engines, social media, e-government etc. Such data centres consist of large collections of servers interconnected using short-reach (reach up to a few hundred meters) optical interconnect. Today, transceivers for these applications achieve up to 100Gb/s by multiplexing 10x 10Gb/s or 4x 25Gb/s channels. In the near future however, data centre operators have expressed a need for optical links which can support 400Gb/s up to 1Tb/s. The crucial challenge is to achieve this in the same footprint (same transceiver module) and with similar power consumption as today’s technology. Straightforward scaling of the currently used space or wavelength division multiplexing may be difficult to achieve: indeed a 1Tb/s transceiver would require integration of 40 VCSELs (vertical cavity surface emitting laser diode, widely used for short‐reach optical interconnect), 40 photodiodes and the electronics operating at 25Gb/s in the same module as today’s 100Gb/s transceiver. Pushing the bit rate on such links beyond today’s commercially available 100Gb/s/fibre will require new generations of VCSELs and their driver and receiver electronics. This work looks into a number of state‐of-the-art technologies and investigates their performance restraints and recommends different set of designs, specifically targeting multilevel modulation formats. Several methods to extend the bandwidth using deep submicron (65nm and 28nm) CMOS technology are explored in this work, while also maintaining a focus upon reducing power consumption and chip area. The techniques used were pre-emphasis in rising and falling edges of the signal and bandwidth extensions by inductive peaking and different local feedback techniques. These techniques have been applied to a transmitter and receiver developed for advanced modulation formats such as PAM-4 (4 level pulse amplitude modulation). Such modulation format can increase the throughput per individual channel, which helps to overcome the challenges mentioned above to realize 400Gb/s to 1Tb/s transceivers