A survey of scan-capture power reduction techniques

With the advent of sub-nanometer geometries, integrated circuits (ICs) are required to be checked for newer defects. While scan-based architectures help detect these defects using newer fault models, test data inflation happens, increasing test time and test cost. An automatic test pattern generator (ATPG) exercise’s multiple fault sites simultaneously to reduce test data which causes elevated switching activity during the capture cycle. The switching activity results in an IR drop exceeding the devices under test (DUT) specification. An increase in IR-drop leads to failure of the patterns and may cause good DUTs to fail the test. The problem is severe during at-speed scan testing, which uses a functional rated clock with a high frequency for the capture operation. Researchers have proposed several techniques to reduce capture power. They used various methods, including the reduction of switching activity. This paper reviews the recently proposed techniques. The principle, algorithm, and architecture used in them are discussed, along with key advantages and limitations. In addition, it provides a classification of the techniques based on the method used and its application. The goal is to present a survey of the techniques and prepare a platform for future development in capture power reduction during scan testing

A Flexible Power Control Method for Right Power Testing of Scan-Based Logic BIST

High power dissipation during scan-based logic BIST is a crucial problem that leads to over-testing. Although controlling test power of a circuit under test (CUT) to an appropriate level is strongly required, it is not easy to control test power in BIST. This paper proposes a novel power controlling method to control the toggle rate of the patterns to an arbitrary level by modifying pseudo random patterns generated by a TPG (Test Pattern Generator) of logic BIST. While many approaches have been proposed to control the toggle rate of the patterns, the proposed approach can provide higher fault coverage. Experimental results show that the proposed approach can control toggle rates to a predetermined target level and modified patterns can achieve high fault coverage without increasing test time.2016 IEEE 25th Asian Test Symposium (ATS), 21-24 Nov. 2016, Hiroshima, Japa

A Hardware Security Solution against Scan-Based Attacks

Scan based Design for Test (DfT) schemes have been widely used to achieve high fault coverage for integrated circuits. The scan technique provides full access to the internal nodes of the device-under-test to control them or observe their response to input test vectors. While such comprehensive access is highly desirable for testing, it is not acceptable for secure chips as it is subject to exploitation by various attacks. In this work, new methods are presented to protect the security of critical information against scan-based attacks. In the proposed methods, access to the circuit containing secret information via the scan chain has been severely limited in order to reduce the risk of a security breach. To ensure the testability of the circuit, a built-in self-test which utilizes an LFSR as the test pattern generator (TPG) is proposed. The proposed schemes can be used as a countermeasure against side channel attacks with a low area overhead as compared to the existing solutions in literature

Low Power BIST for Scan-Shift and Capture Power

Low-power test technology has been investigated deeply to achieve an accurate and efficient testing. Although many sophisticated methods are proposed for scan-test, there are not so many for logic BIST because of its uncontrollable randomness. However, logic BIST currently becomes vital for system debug or field test. This paper proposes a novel low power BIST technology that reduces shift-power by eliminating the specified high-frequency parts of vectors and also reduces capture power. The authors show that the proposed technology not only reduces test power but also keeps test coverage with little loss.2012 IEEE 21st Asian Test Symposium, 19-22 Nov. 2012, Niigata, Japa

Interictal Network Dynamics in Paediatric Epilepsy Surgery

Epilepsy is an archetypal brain network disorder. Despite two decades of research elucidating network mechanisms of disease and correlating these with outcomes, the clinical management of children with epilepsy does not readily integrate network concepts. For example, network measures are not used in presurgical evaluation to guide decision making or surgical management plans. The aim of this thesis was to investigate novel network frameworks from the perspective of a clinician, with the explicit aim of finding measures that may be clinically useful and translatable to directly benefit patient care. We examined networks at three different scales, namely macro (whole brain diffusion MRI), meso (subnetworks from SEEG recordings) and micro (single unit networks) scales, consistently finding network abnormalities in children being evaluated for or undergoing epilepsy surgery. This work also provides a path to clinical translation, using frameworks such as IDEAL to robustly assess the impact of these new technologies on management and outcomes. The thesis sets up a platform from which promising computational technology, that utilises brain network analyses, can be readily translated to benefit patient care

Design and application of reconfigurable circuits and systems

Open Acces

Quiescent current testing of CMOS data converters

Power supply quiescent current (IDDQ) testing has been very effective in VLSI circuits designed in CMOS processes detecting physical defects such as open and shorts and bridging defects. However, in sub-micron VLSI circuits, IDDQ is masked by the increased subthreshold (leakage) current of MOSFETs affecting the efficiency of I¬DDQ testing. In this work, an attempt has been made to perform robust IDDQ testing in presence of increased leakage current by suitably modifying some of the test methods normally used in industry. Digital CMOS integrated circuits have been tested successfully using IDDQ and IDDQ methods for physical defects. However, testing of analog circuits is still a problem due to variation in design from one specific application to other. The increased leakage current further complicates not only the design but also testing. Mixed-signal integrated circuits such as the data converters are even more difficult to test because both analog and digital functions are built on the same substrate. We have re-examined both IDDQ and IDDQ methods of testing digital CMOS VLSI circuits and added features to minimize the influence of leakage current. We have designed built-in current sensors (BICS) for on-chip testing of analog and mixed-signal integrated circuits. We have also combined quiescent current testing with oscillation and transient current test techniques to map large number of manufacturing defects on a chip. In testing, we have used a simple method of injecting faults simulating manufacturing defects invented in our VLSI research group. We present design and testing of analog and mixed-signal integrated circuits with on-chip BICS such as an operational amplifier, 12-bit charge scaling architecture based digital-to-analog converter (DAC), 12-bit recycling architecture based analog-to-digital converter (ADC) and operational amplifier with floating gate inputs. The designed circuits are fabricated in 0.5 μm and 1.5 μm n-well CMOS processes and tested. Experimentally observed results of the fabricated devices are compared with simulations from SPICE using MOS level 3 and BSIM3.1 model parameters for 1.5 μm and 0.5 μm n-well CMOS technologies, respectively. We have also explored the possibility of using noise in VLSI circuits for testing defects and present the method we have developed

Micro/Nano Manufacturing

Micro manufacturing involves dealing with the fabrication of structures in the size range of 0.1 to 1000 µm. The scope of nano manufacturing extends the size range of manufactured features to even smaller length scales—below 100 nm. A strict borderline between micro and nano manufacturing can hardly be drawn, such that both domains are treated as complementary and mutually beneficial within a closely interconnected scientific community. Both micro and nano manufacturing can be considered as important enablers for high-end products. This Special Issue of Applied Sciences is dedicated to recent advances in research and development within the field of micro and nano manufacturing. The included papers report recent findings and advances in manufacturing technologies for producing products with micro and nano scale features and structures as well as applications underpinned by the advances in these technologies

Doctor of Philosophy

dissertationThe human brain is the seat of cognition and behavior. Understanding the brain mechanistically is essential for appreciating its linkages with cognitive processes and behavioral outcomes in humans. Mechanisms of brain function categorically represent rich and widely under-investigated biological substrates for neural-driven studies of psychiatry and mental health. Research examining intrinsic connectivity patterns across whole brain systems utilizes functional magnetic resonance imaging (fMRI) to trace spontaneous fluctuations in blood oxygen-level dependent (BOLD) signals. In the first study presented, we reveal patterns of dynamic attractors in resting state functional connectivity data corresponding to well-documented biological networks. We introduce a novel simulation for whole brain dynamics that can be adapted to either group-level analysis or single-subject level models. We describe stability of intrinsic functional architecture in terms of transient and global steady states resembling biological networks. In the second study, we demonstrate plasticity in functional connectivity following a minimum six-week intervention to train cognitive performance in a speed reading task. Long-term modulation of connectivity with language regions indicate functional connectivity as a candidate biomarker for tracking and measuring functional changes in neural systems as outcomes of cognitive training. The third study demonstrates utility of functional biomarkers in predicting individual differences in behavioral and cognitive features. We successfully predict three major domains of personality psychologyintelligence, agreeableness, and conscientiousnessin individual subjects using a large (N=475) open source data sample compiled by the National Institutes of Healths Human Connectome Project

Measurement of allocentric processing in mild cognitive impairment and early Alzheimer’s disease using a virtual reality object location paradigm

Aim: Mild cognitive impairment (MCI) and Alzheimer’s Disease (AD) are major contributors to disability in old age and defined in the early stages by spatial memory deficits associated with hippocampal (HC) and entorhinal (EC) atrophy. Currently diagnosis occurs late in the process which limits efficacy of interventions. This study investigated the neural correlates of a novel object location task (OLT) in immersive virtual reality (iVR). Methods: Twenty amnestic MCI (aMCI) patients and twenty two healthy controls were tested on the iVR OLT, underwent neuropsychological testing and structural MRI scanning. OLT performance and HC, EC subfield volumetric data were compared between groups, and correlational analyses of HC/EC volumes and performance were conducted. Results: Participants with aMCI were significantly impaired in object location recall and object recognition compared to controls. They had significantly smaller total HC, subiculum, CA1, EC and perirhinal volumes. There was a significant interaction of group in analysis of neural correlates: OLT performance was strongly predicted by total HC and subiculum volumes in patients only. EC subfields were not significant predictors of performance. Conclusion: Performance on the novel OLT in immersive VR is a good indicator of HC integrity in older adults with amnestic MCI and can improve the diagnostic process for people with MCI and AD in the future