The Belle II DEPFET Pixel Vertex Detector : Development of a Full-Scale Module Prototype

The Belle II experiment, which will start after 2015 at the SuperKEKB accelerator in Japan, will focus on the precision measurement of the CP-violation mechanism and on the search for physics beyond the Standard Model. A new detection system with an excellent spatial resolution and capable of coping with considerably increased background is required. To address this challenge, a pixel detector based on DEPFET technology has been proposed. A new all silicon integrated circuit, called Data Handling Processor (DHP), is implemented in 65 nm CMOS technology. It is designed to steer the detector and preprocess the generated data. The scope of this thesis covers DHP tests and optimization as well the development of its test environment, which is the first Full-Scale Module Prototype of the DEPFET Pixel Vertex detector

Topical Workshop on Electronics for Particle Physics

The purpose of the workshop was to present results and original concepts for electronics research and development relevant to particle physics experiments as well as accelerator and beam instrumentation at future facilities; to review the status of electronics for the LHC experiments; to identify and encourage common efforts for the development of electronics; and to promote information exchange and collaboration in the relevant engineering and physics communities

Characterization of radiation-hard monolithic CMOS sensors

The work presented in this thesis consists of the characterisation of monolithic CMOS sensors targeting the requirements of the outer-most layer of the ATLAS Inner Tracker after the High Luminosity upgrade of the Large Hadron Collider. Three detectors are investigated: an investigator chip and two large scale demonstrators (MALTA and mini-MALTA). The investigator chip is designed in the standard TowerJazz 180 nm technology and served as a tool to investigate the geometric parameters that affect the pixel capacitance. The MALTA chip is designed in the modified TowerJazz 180 nm technology and implements a novel asynchronous readout to minimise power consumption. The sensor is irradiated with X-rays up to 1.25 MRad to test the resistance of the front-end circuit to ionising radiation effects. The mini-MALTA chip is designed following the results obtained on MALTA and implements an improved front-end and pixel layout to enhance the radiation hardness of MALTA. A similar X-ray irradiation campaign is done for this chip showing good radiation hardness after 80 MRad of TID. Aside from the characterisation work, FPGA-based readouts for the MALTA and mini-MALTA chips were developed in collaboration with the CMOS development group at CERN

Design of a Low-Cost Passive UHF RFID tag in 0.18um CMOS technology

The work addresses the design of a passive UHF Radio-Frequency Identification (RFID) tag. In order to realize a product able to be competitive in the RFID expanding market, a cost reduction policy has been applied in the design: a general purpose digital technology has been employed, resorting to specific techniques in order to overcome the limitations due to the lack of process options. Such solutions are accurately described, and every block composing the transponder analog frontend is analyzed, highlighting advantages and disadvantages of the proposed architectures with respect to the ones present in literature. The circuits theory is validated through simulations and experimental data.Il lavoro di tesi è imperniato sul progetto di un tag passivo per l'Identificazione a Radio-Frequenza (RFID) operante nelle bande UHF. Per il progetto è stata applicata una politica di riduzione dei costi, così da proporre un prodotto in grado di essere competitivo nel fiorente mercato dell'RFID: è stata scelta una tecnologia digitale general-purpose, e specifiche tecniche di progettazione sono state utilizzate per superare le limitazioni dovute alla scarsità di opzioni di processo. Le soluzioni adottate sono descritte accuratamente, ed è riportata l'analisi di ogni singolo blocco componente il frontend analogico, evidenziando vantaggi e svantaggi delle architetture proposte rispetto a quelle presenti in letteratura. La validità della teoria alla base dei circuiti è stata verificata tramite simulazioni e dati sperimentali

The CMS experiment at the CERN LHC

The Compact Muon Solenoid (CMS) detector is described. The detector operates at the Large Hadron Collider (LHC) at CERN. It was conceived to study proton-proton (and leadlead) collisions at a centre-of-mass energy of 14 TeV (5.5 TeV nucleon-nucleon) and at luminosities up to 1034 cm-2s-1 (1027 cm-2s-1). At the core of the CMS detector sits a high-magnetic field and large-bore superconducting solenoid surrounding an all-silicon pixel and strip tracker, a lead-tungstate scintillating-crystals electromagnetic calorimeter, and a brass-scintillator sampling hadron calorimeter. The iron yoke of the flux-return is instrumented with four stations of muon detectors covering most of the 4π solid angle. Forward sampling calorimeters extend the pseudorapidity coverage to high values (|η| ≤ 5) assuring very good hermeticity. The overall dimensions of the CMS detector are a length of 21.6 m, a diameter of 14.6 m and a total weight of 12500 t

Design and validation of key components for the readout electronics of future PET scanners

This thesis work discusses the design and validation of two circuit components used in the electronic readout of positron emission tomography (PET) scanners for biomedical applications: a constant fraction discriminator (CFD) and an integrated CMOS time to digital converter (TDC). The former is used in the read out of a double-head PET scanner already developed by the group of medical physics at INFN Pisa for non-invasive dose delivery monitoring in hadrontherapy. The goal of the work has been the optimization of the front-end PCB in terms of timing performances so as to reduce the dead time and resolution at system level. A new CFD board has been implemented and experimental results have shown a significant enhancement of the timing characteristics which have enabled performing in-beam PET data acquisition which is fundamental in hadrontherapy treatment. The design of an integrated CMOS TDC to be used for the time of flight measurement in a magnetic field-compatible PET block detector is the second topic of the thesis. The required time resolutions, linear behaviour as well as the communication with other readout elements have been taken into account in the definition of the circuit topology. Cadence and Verilog simulations have shown that a bin size of 100 ps can be obtained with the combination of a submicron technology (UMC 65 nm LLLVT) and a pipeline approach where a 10 bit systolic counter coupled to a 4 stage delay locked loop (DLL) are exploited. This translates into a nominal resolution of 29 ps. In addition, the use of a short DLL leads to a high linearity which is an issue in PET measurements. Despite lower resolutions are obtained in literature with different TDC topologies, achieving good performances in terms of both time resolution and linearity is not straightforward. The converter also features a real-time validation algorithm which is capable to reject noise inputs generated by the photodetector without impairing the acquisition capability of the system. A standard-cell unit has been also designed which is in charge of data buffering and serial communication with external readout boards. A 47 bit output word is provided by the semi-custom stage at a measurement rate which is selectable between 31.25 MHz and 62.5 MHz with a double hit resolution of 170 ns. An 8 channel prototype of 1.875 x 1.875 mm2 has been submitted in March 2013 in order to validate simulated data with experimental results

Solid State Circuits Technologies

The evolution of solid-state circuit technology has a long history within a relatively short period of time. This technology has lead to the modern information society that connects us and tools, a large market, and many types of products and applications. The solid-state circuit technology continuously evolves via breakthroughs and improvements every year. This book is devoted to review and present novel approaches for some of the main issues involved in this exciting and vigorous technology. The book is composed of 22 chapters, written by authors coming from 30 different institutions located in 12 different countries throughout the Americas, Asia and Europe. Thus, reflecting the wide international contribution to the book. The broad range of subjects presented in the book offers a general overview of the main issues in modern solid-state circuit technology. Furthermore, the book offers an in depth analysis on specific subjects for specialists. We believe the book is of great scientific and educational value for many readers. I am profoundly indebted to the support provided by all of those involved in the work. First and foremost I would like to acknowledge and thank the authors who worked hard and generously agreed to share their results and knowledge. Second I would like to express my gratitude to the Intech team that invited me to edit the book and give me their full support and a fruitful experience while working together to combine this book