Simulation of FinFET Structures

The intensive downscaling of MOS transistors has been the major driving force behind the aggressive increases in transistor density and performance, leading to more chip functionality at higher speeds. While on the other side the reduction in MOSFET dimensions leads to the close proximity between source and drain, which in turn reduces the ability of the gate electrode to control the potential distribution and current flow in the channel region and also results in some undesirable effects called the short-channel effects. These limitations associated with downscaling of MOSFET device geometries have lead device designers and researchers to number of innovative techniques which include the use of different device structures, different channel materials, different gate-oxide materials, different processes such as shallow trench isolation, source/drain silicidation, lightly doped extensions etc. to enable controlled device scaling to smaller dimensions. A lot of research and development works have been done in these and related fields and more remains to be carried out in order to exploit these devices for the wider applications

Compact modeling of thin-film silicon transistors fabricated on glass

The semiconductor industry, now entering its seventh decade, continues to innovate and evolve at a breakneck pace. E. O. Wilson, the famous Harvard biologist who is an expert on ants, estimates that there are 1017 ants on earth. The semiconductor industry is now shipping 100 transistors per ant every year. In addition, the pace of growth means we are building more electronics in a year than existed on January 1st of that year! A major driver for this growth in recent years is the portable consumer electronics market which includes cell phones, personal digital assistants, and tablets. The focus of this dissertation is centered on a new thin-film silicon technology on glass introduced by Corning Inc., and targeted to meet the needs of the portable product display market. The work presented in this dissertation revolves around a new technology developed by Corning Inc. known as Silicon on Glass or SiOG which permits the transfer of a thin single-crystal silicon film to a glass substrate. This technology coupled with a low-temperature CMOS process has the potential to create devices with performance characteristics rivaling those developed using conventional bulk CMOS processes. These higher performing devices permit an increased level of circuit integration directly on the glass substrate and have the potential to enable new display technologies such as OLED (Organic Light Emitting Diode). The SiOG CMOS devices are distinctly different from traditional thin-film, silicon-on-insulator, and bulk CMOS devices in that they rely on both surface and bulk conduction. Furthermore, their current-voltage characteristics are heavily influenced by fringing electric fields in the glass substrate. This dissertation presents an overview of display technology as well as a review of computer- aided design tools for integrated circuit development with a focus on compact modeling. In addition, some early work on developing advanced OLED display driver circuits using SiOG technology is presented.The bulk of this dissertation is focused on the development of compact models which properly describe the electrical characteristics of SiOG CMOS devices. For all but the most trivial cases, the set of coupled nonlinear partial differential equations that describe semiconductor device behavior has not been solved analytically. Even when the semiconductor equations that represent current flow, charge distribution, and potential distribution are decoupled and device-specific simplifications are applied, analytic solutions remain elusive. Two different methods for developing compact models for the SiOG CMOS devices are presented with distinct methods for developing approximate solutions. In addition, a model for the fringing electric field is developed using conformal mapping techniques, and its effect on drain current is explored. Finally, a new technique for solving the nonlinear semiconductor equations is explored. The application of a new mathematical technique known as the Homotopy Analysis Method (HAM) is presented as it relates to the general Poisson\u27s equation for semiconductor devices

ANALYTICAL COMPACT MODELING OF NANOSCALE MULTIPLE-GATE MOSFETS.

L’objectiu principal d’aquest treball és el desenvolupament d’un model compacte per a MOSFETs de múltiple porta d’escala nanomètrica, que sigui analític, basat en la física del dispositiu, i predictiu per a simulacions AC i DC. Els dispositius investigats són el MOSFET estàndar en mode d’inversió, a més d’un nou dispositiu anomenat “junctionless MOSFET” (MOSFET sense unions). El model es va desenvolupar en una formulació compacta amb l’ajuda de l’equació de Poisson i la tècnica de la transformación conforme de Schwarz-Cristoffel. Es varen obtenir les equacions del voltatge llindar i el pendent subllindar. Usant la funció W de Lambert, a més d’una funció de suavització per a la transcició entre les regions de depleció i acumulació, s’obté un model unificat de la densitat de càrrega, vàlid per a tots els modes d’operació del transistor. S’estudien també les dependències entre els paràmetres físics del dispositiu i el seu impacte en el seu rendiment. Es tenen en compteefectes importants de canal curt i de quantització. Es discuteixen també la simetria al voltant de Vds= 0 V, i la continuïtat del corrent de drenador en les derivades d’ordre superior. El model va ser validat mitjançant simulacions TCAD numèriques i mesures experimentals.El objetivo principal de este trabajo es el desarrollo de un modelo compacto para MOSFETs de múltiple puerta de escala nanométrica, que sea analítico, basado en la física del dispositivo, y predictivo para simulaciones AC y DC. Los dispositivos investigados son el MOSFET estándar en modo inversión, además de un nuevo dispositivo llamado “junctionless MOSFET” (MOSFET sin uniones). El modelo se desarrolló en una formulación compacta con la ayuda de la ecuación de Poisson y la técnica de transformación conforme de Schwarz-Cristoffel. Se obtuvieron las ecuaciones del voltaje umbral y la pendiente subumbral. Usando la función W de Lambert, además de una función de suavización para la transición entre las regiones de depleción y acumulación, se obtiene un modelo unificado de la densidad de carga, válido para todos los modos de operación del transistor. Se estudian también las dependencias entre los parámetros físicos del dispositivo y su impacto en su rendimiento. Se tienen en cuenta efectos importantes de canal corto y de cuantización. Se discuten también la simetría alrededor de Vds= 0 V, y la continuidad de la corriente de drenador en las derivadas de orden superior. El modelo fue validado mediante simulaciones TCAD numéricas y medidas experimentales.The main focus is on the development of an analytical, physics-based and predictive DC and AC compact model for nanoscale multiple-gate MOSFETs. The investigated devices are the standard inversion mode MOSFET and a new device concept called junctionless MOSFET. The model is derived in closed-from with the help of Poisson's equation and the conformal mapping technique by Schwarz-Christoffel. Equations for the calculation of the threshold voltage and subthreshold slope are derived. Using Lambert's W-function and a smoothing function for the transition between the depletion and accumulation region, an unified charge density model valid for all operating regimes is developed. Dependencies between the physical device parameters and their impact on the device performance are worked out. Important short-channel and quantization effects are taken into account. Symmetry around Vds = 0 V and continuity of the drain current at derivatives of higher order are discussed. The model is validated versus numerical TCAD simulations and measurement data

SYNTHESIS AND EVALUATION OF ANTIMICROBIAL ACTIVITY OF PHENYL AND FURAN-2-YL[1,2,4] TRIAZOLO[4,3-a]QUINOXALIN-4(5H)-ONE AND THEIR HYDRAZONE PRECURSORS

A variety of 1-(s-phenyl)-[1,2,4]triazolo[4,3-a]quinoxalin-4(5H)-one (3a-3h) and 1-(s-furan-2-yl)-[1,2,4]triazolo[4,3- a]quinoxalin-4(5H)-one (5a-d) were synthesized from thermal annelation of corresponding hydrazones (2a-h) and (4a-d) respectively in the presence of ethylene glycol which is a high boiling solvent. The structures of the compounds prepared were confirmed by analytical and spectral data. Also, the newly synthesized compounds were evaluated for possible antimicrobial activity. 3-(2-(4-hydroxylbenzylidene)hydrazinyl)quinoxalin-2(1H)-one (2e) was the most active antibacterial agent while 1-(5-Chlorofuran-2-yl)-[1,2,4]triazolo[4,3-a]quinoxalin-4(5H)-one (5c) stood out as the most potent antifungal agent

Phase Noise Analyses and Measurements in the Hybrid Memristor-CMOS Phase-Locked Loop Design and Devices Beyond Bulk CMOS

Phase-locked loop (PLLs) has been widely used in analog or mixed-signal integrated circuits. Since there is an increasing market for low noise and high speed devices, PLLs are being employed in communications. In this dissertation, we investigated phase noise, tuning range, jitter, and power performances in different architectures of PLL designs. More energy efficient devices such as memristor, graphene, transition metal di-chalcogenide (TMDC) materials and their respective transistors are introduced in the design phase-locked loop. Subsequently, we modeled phase noise of a CMOS phase-locked loop from the superposition of noises from its building blocks which comprises of a voltage-controlled oscillator, loop filter, frequency divider, phase-frequency detector, and the auxiliary input reference clock. Similarly, a linear time-invariant model that has additive noise sources in frequency domain is used to analyze the phase noise. The modeled phase noise results are further compared with the corresponding phase-locked loop designs in different n-well CMOS processes. With the scaling of CMOS technology and the increase of the electrical field, the problem of short channel effects (SCE) has become dominant, which causes decay in subthreshold slope (SS) and positive and negative shifts in the threshold voltages of nMOS and pMOS transistors, respectively. Various devices are proposed to continue extending Moore\u27s law and the roadmap in semiconductor industry. We employed tunnel field effect transistor owing to its better performance in terms of SS, leakage current, power consumption etc. Applying an appropriate bias voltage to the gate-source region of TFET causes the valence band to align with the conduction band and injecting the charge carriers. Similarly, under reverse bias, the two bands are misaligned and there is no injection of carriers. We implemented graphene TFET and MoS2 in PLL design and the results show improvements in phase noise, jitter, tuning range, and frequency of operation. In addition, the power consumption is greatly reduced due to the low supply voltage of tunnel field effect transistor

Out-of-Equilibrium Carrier Dynamics in Graphene and Graphene-based Devices for High-Performance Electronics

[ES]Con los límites tecnológicos de las tecnologías de semiconductores tradicionales alcanzando los límites de escalado y integración en chip, el descubrimiento del grafeno y sus impresionantes propiedades supuso una prometedora alternativa para el futuro de la electrónica. Para contextualizar adecuadamente las posibilidades del grafeno, la investigación de las propiedades micrsocópicas del transporte electrónico es una tarea crucial. Con este objetivo, se ha desarrollado un simulador Monte Carlo para grafeno, que incluye la dinámica de electrones y huecos, con espacial atención a fenómenos de portadores calientes, como fonones fuera de equilibrio, procesos Auger o generación/recombinación asistida por fonones. El análisis del transporte electrónico a campos altos permitió cuantificar el impacto relativo del autocalentamiento y los fonones calientes sobre la velocidad de deriva en condiciones estacionarias y la temperatura del material. Además se observó un comportamiento lineal de la corriente debida a la ionización por impacto. Se ha estudiado la fenomenología relacionada con fluctuaciones empleando diversos métodos numéricos orientados a condiciones transitorias particulares (saltos abruptos de campo o señales AC). La temperatura del ruido dependiente de la frecuencia se obtuvo a partir de la difusividad y movilidad diferencial los portadores, y la viabilidad de la generación de armónicos de orden alto en grafeno se presenta en términos del ancho de banda límite para su detección. El potencial del grafeno para aplicaciones optoelectrónicas precisa de una comprensión detallada de los procesos de relajación ultrarrápida que sufren los portadores fotoexcitados con longitudes de onda apropiadas. Llevamos a cabo un examen exhaustivo de este proceso, con especial atención a las condiciones iniciales de fotoexcitación, el papel de los fonones calientes, y el efecto del sustrato. Finalmente presentamos una versión inicial de simulador para dispositivos electrónicos basados en materiales 2D, que cimentará las líneas futuras de investigación en el campo del modelado Monte Carlo de estos dispositivos.[EN] With traditional semiconductor technology approaching the limits of scaling and chip integration, the discovery of graphene and its astonishing properties stood as a promising alternative for future electronics. In order to adequately put into context the possibilities of graphene, it is critical to investigate the microscopic properties of electronic transport in this material. With this objective, a Monte Carlo simulator for graphene that includes the dynamics of electrons and holes, with especial focus on hot carrier phenomena, like hot phonons, Auger processes, and phonon-assisted generation and recombination mechanisms has been developed. The analysis of electronic transport at high fields allowed to quantify the relative impact that self heating and hot phonons have in the steady state drift velocity of the carriers and temperature. Linear sheet current behavior at high fields was found to be the result of free charge carriers created through impact ionization collisions. Velocity fluctuation phenomena in graphene were studied employing various numerical methods aimed at the analysis of specific transient dynamics (under the application of switching or AC electric fields). The frequency-dependent noise temperature was obtained from the diffusivity an differential mobility, and the feasibility of generating high-order harmonics in graphene, was presented in terms of the detection bandwidth. The potential of graphene for optoelectronic applications requires also a deep understanding of the ultrafast relaxation processes that carriers undergo after being exposed to light with an adequate wavelength. A thorough exploration of this process, with particular focus on the initial photoexcitation conditions, the effect of out-of-equilibrium phonons and the influence of an underlying substrate is presented, together with an experimental pump and probe differential transmission spectroscopy approach. An initial version of a simulator of 2D material-based devices is presented, which allows to set the basis for future research in the field of Monte Carlo modeling of this kind of electronic devices

Charge-Based Compact Modeling of Capacitances and Low-Frequency Noise in Organic Thin-Film Transistors

Els transistors orgànics de capa prima són candidats prometedors per a noves aplicacions electròniques a causa de la possibilitat de fabricar dispositius electrònics orgànics a baixes temperatures sobre substrats flexibles com el plàstic o el paper. Aquesta tesi doctoral tracta del desenvolupament d'un model compacte basat en la càrrega per a la descripció del comportament capacitiu i del soroll de baixa freqüència en transistors orgànics de capa prima. A partir d'un model de corrent continu existent, es deriven expressions per a les càrregues totals en condicions d'operació quasi estàtica. Els efectes no quasistàtics es capturen mitjançant diferents mètodes, com ara l'enfocament de segmentació de canals o funcions d'escalat depenents de la freqüència de les àrees del transistor on es calculen les càrregues. El model de les càrregues totals es verifica mitjançant mesures de capacitat d'un TFT orgànic esglaonat i per simulacions numèriques de TFT orgànics en les arquitectures esglaonades i coplanars mitjançant el simulador de dispositiu Sentaurus TCAD. Els models no quasistàtics es verifiquen mitjançant mesures d'admitància depenents de la freqüència d'un transistor esglaonat i per mesures de paràmetres de dispersió de transistors coplanars i esglalonats. El model compacte s'implementa en el llenguatge de descripció de hardware Verilog-A i la simulació d'un amplificador diferencial es compara amb les mesures, amb les quals es mostra un bon acord. El model de soroll es verifica mitjançant mesures de TFT orgànics esglalonats i simulacions TCAD. El model compacte mostra en general una bona concordança i flexibilitat en general pel que fa a l'arquitectura del dispositiu (per exemple, esglaonat o coplanar) i els materials utilitzats.Los transistores orgánicos de capa fina son candidatos prometedores para nuevas aplicaciones electrónicas debido a la posibilidad de fabricar dispositivos electrónicos orgánicos a bajas temperaturas en sustratos flexibles como plástico o papel. Esta tesis doctoral trata del desarrollo de un modelo compacto basado en la carga para la descripción del comportamiento capacitivo y el ruido de baja frecuencia en transistores orgánicos de capa fina. A partir de un modelo DC existente, se desarrollan expresiones para las cargas totales en condiciones de operación cuasiestáticas. Los efectos no cuasiestáticos se capturan mediante diferentes métodos, como la aproximación de segmentación del canal o las funciones de escalado dependientes de la frecuencia de las áreas del transistor donde se calculan las cargas. El modelo para las cargas totales se verifica mediante medidas de capacitancia de un TFT orgánico escalonado y mediante simulaciones numéricas de TFT orgánicos en las arquitecturas escalonada y coplanar utilizando el simulador de dispositivo TCAD Sentaurus. Los modelos no cuasiestáticos se verifican mediante medidas de admitancia dependientes de la frecuencia de un transistor escalonado y mediante medidas de parámetros de dispersión de transistores coplanares y escalonados. El modelo compacto se implementó en el lenguaje de descripción de hardware Verilog-A y la simulación de un amplificador diferencial se compara con medidas, observándose una buena concordancia. El modelo de ruido se verifica mediante medidas de TFT orgánicos escalonados y mediante simulaciones TCAD. El modelo compacto muestra en general una buena concordancia y flexibilidad con respecto a la arquitectura del dispositivo (p. ej. escalonado o coplanar) y los materiales utilizados.Organic thin-film transistors are promising candidates for novel electronics applications due to the possibility of fabricating organic electronic devices at low temperatures on flexible substrates like plastic or paper. This doctoral thesis deals with the development of a charge-based compact model for the description of the capacitive behavior and the low-frequency noise in organic thin-film transistors. Based on an existing DC model, expressions for the total charges under quasistatic operation conditions are derived. Non-quasistatic effects are captured by different methods, such as the channel-segmentation approach or frequency-dependent scaling functions of the areas in the transistor where charges are calculated. The model for the total charges is verified by capacitance measurements of a staggered organic TFT and by numerical simulations of organic TFTs in the staggered and coplanar architectures using the device simulator Sentaurus TCAD. The non-quasistatic models are verified by frequency-dependent admittance measurements of a staggered transistor and by scattering-parameter measurements of coplanar and staggered transistors. The compact model is implemented in the hardware description language Verilog-A and the simulation of a differential amplifier is compared to measurements, which shows a good agreement. The noise model is verified by measurements of staggered organic TFTs and by TCAD simulations. The compact model shows an overall good agreement and flexibility with respect to the device architecture (e. g. staggered or coplanar) and the used materials

Electronic Nanodevices

The start of high-volume production of field-effect transistors with a feature size below 100 nm at the end of the 20th century signaled the transition from microelectronics to nanoelectronics. Since then, downscaling in the semiconductor industry has continued until the recent development of sub-10 nm technologies. The new phenomena and issues as well as the technological challenges of the fabrication and manipulation at the nanoscale have spurred an intense theoretical and experimental research activity. New device structures, operating principles, materials, and measurement techniques have emerged, and new approaches to electronic transport and device modeling have become necessary. Examples are the introduction of vertical MOSFETs in addition to the planar ones to enable the multi-gate approach as well as the development of new tunneling, high-electron mobility, and single-electron devices. The search for new materials such as nanowires, nanotubes, and 2D materials for the transistor channel, dielectrics, and interconnects has been part of the process. New electronic devices, often consisting of nanoscale heterojunctions, have been developed for light emission, transmission, and detection in optoelectronic and photonic systems, as well for new chemical, biological, and environmental sensors. This Special Issue focuses on the design, fabrication, modeling, and demonstration of nanodevices for electronic, optoelectronic, and sensing applications