Multi-channel, low nonlinearity time-to-digital converters based on 20nm and 28nm FPGAs

Abstract—This paper presents low nonlinearity, compact and multi-channel time-to-digital converters (TDC) in Xilinx 28nm Virtex 7 and 20nm UltraScale FPGAs. The proposed TDCs integrate several innovative methods that we have developed: 1) the sub-tapped delay line (TDL) averaging topology, 2) tap timing tests, 3) a direct compensation architecture and 4) a mixed calibration method. The code density tests show that the proposed TDCs have much better linearity performances than previously reported ones. Our approach is cost-effective in terms of the consumption of logic resources. To demonstrate this, we implemented 96 channel TDCs in both FPGAs, using less than 25 % of the logic resources. The achieved least significant bit (LSB) is 10.5ps for Virtex 7 and 5.0 ps for UltraScale FPGAs. After the compensation and calibration, the differential nonlinearity (DNL) is within [-0.05, 0.08] LSB with σDNL = 0.01 LSB, and the integral nonlinearity (INL) is within [-0.09, 0.11] LSB with σINL = 0.04 LSB for the Virtex 7 FPGA. The DNL is within [-0.12, 0.11] LSB with σDNL = 0.03 LSB, and the INL is within [-0.15, 0.48] LSB with σINL = 0.20 LSB for the UltraScale FPGA

TIME-DIFFERENCE CIRCUITS: METHODOLOGY, DESIGN, AND DIGITAL REALIZATION

This thesis presents innovations for a special class of circuits called Time Difference (TD) circuits. We introduce a signal processing methodology with TD signals that alters the target signal from a magnitude perspective to time interval between two time events and systematically organizes the primary TD functions abstracted from existing TD circuits and systems. The TD circuits draw attention from a broad range of application fields. In addition, highly evolved complementary metal-oxide-semiconductor (CMOS) technology suffers from various problems related to voltage and current amplitude signal processing methods. Compared to traditional analog and digital circuits, TD circuits bring several compelling features: high-resolution, high-throughput, and low-design complexity with digital integration capability. Further, the fabrication technology is advancing into the nanometer regime; the reduction in voltage headroom limits the performance of traditional analog/mixed-signal designs. All-digital design of time-difference circuit needs to be stressed to adapt to the low-cost, low-power, and high-portability applications. We focus on Time-to-Digital Converters (TDC), one of the crucial building blocks in TD circuits. A novel algorithmic architecture is proposed based on a binary search algorithm and validated with both simulation and fabricated silicon. An all-digital structure Time-difference Amplifier (TDA) is designed and implemented to make FPGA and other all-digital implementations for TDC and related TD circuits feasible. Besides, we propose an all-digital timing measurement circuit based on the process variation from CMOS fabrication: PVTMC, which achieves a high measurement resolution:

Conception d'un convertisseur temps-numérique dédié aux applications de tomographie optique diffuse en technologie CMOS 130 nm

La mesure de temps de vol de photons et/ou de temps de propagation d’ondes RF et ultra large bande est devenue une technique essentielle et indispensable pour de nombreuses applications telles qu’en géolocalisation en intérieur, en détection LASER et en imagerie biomédicale, notamment en tomographie optique diffuse (TOD) avec des mesures dans le domaine temporel (DT). De telles mesures nécessitent des convertisseurs temps-numérique aptes à mesurer des intervalles de temps très courts avec grande précision, et ce, à des résolutions temporelles allant de quelques picosecondes à quelques dizaines de picosecondes. Les scanners TOD-DT ont généralement recours à des cartes électroniques de comptage de photons uniques intégrant essentiellement des convertisseurs temps-numérique hybrides (un mixte de circuits monolithiques et non-monolithiques). Dans le but de réduire le temps d’acquisition de ces appareils et d’augmenter leur précision, plusieurs mesures à différentes positions et longueurs d’ondes doivent pouvoir être effectuées en parallèle, ce qui exige plusieurs cartes de comptage de photons. L’implémentation de tels dispositifs en technologie CMOS apporte de multiples avantages particulièrement en termes de coût, d’intégration et de consommation de puissance. Cette thèse apporte une solution architecturale d’un convertisseur temps-numérique à 10-bits dédié aux applications de TOD-DT. Le convertisseur réalisé en technologie CMOS 0,13 μm d’IBM et occupant une surface en silicium de 1,83 x 2,23 mm[indice supérieur 2] incluant les plots de connexion, présente une résolution temporelle de 12 ps sur une fenêtre de 12 ns pour une consommation en courant de 4,8 mA. Les avantages de l’architecture proposée par rapport à d’autres réalisations rapportées dans la littérature résident dans son immunité face aux variations globales du procédé de fabrication, l’indépendance de la résolution temporelle vis-à-vis de la technologie ciblée et la faible gigue temporelle qu’il présente. Le circuit intégré réalisé trouvera plusieurs champs d’applications autres que la TOD notamment dans les tomographes d’émission par positrons, les boucles à verrouillage de phase numériques et dans les systèmes de télédétection et d’imagerie 3D

Analysis, Quantification, and Discussion of the Approximations Introduced by Pulsed 3-D LiDARs

Light detection and rangings (LiDARs) are considered essential for the environmental sensing required by most advanced driver assistance system (ADAS), including autonomous driving. This has led to significant investments resulted in the availability of countless measuring systems that are increasingly performing and less expensive. Nevertheless, the extremely high speed of light still leads to a nonnegligible quantization error in the direct time-of-flight (ToF) measure at the base of pulsed LiDARs-the leading technology for automotive applications. Hence, pulsed 3-D LiDARs analyze the surrounding by approximating and deforming it on concentric spheres whose radii are quantized with a quantization step that, for most commercial systems, is on the order of some centimeters. The deformation and error introduced by such quantization can thus he significant. In this study, we point out the approximations and assumptions intrinsic to 3-D LiDARs and propose a measurement procedure that, through the analysis of the fine variations of the target position, allows an accurate investigation of the axial resolution and error-probably among the few limitations still affecting this technology. To the best of our knowledge, this is the first study focused on the detailed analysis of the quantization error in 3-D LiDARs. The proposed method has been tested on one of the most popular 3-D LiDARs, namely the MRS 6000 by Sick. The obtained results revealed for the MRS 6000 a quantization step of about 6 cm (ToF quantization of about 0.4 ns) and an axial error normally distributed with experimental standard deviation of about 30 mm

NASA Tech Briefs Index, 1978

Approximately 601 announcements of new technology derived from the research and development activities of the National Aeronautics and Space Administration are presented. Emphasis is placed on information considered likely to be transferrable across industrial, regional, or disciplinary lines. Subject matter covered includes: electronic components and circuits; electron systems; physical sciences; materials; life sciences; mechanics; machinery; fabrication technology; and mathematics and information sciences

A Sub-10ps Time-to-Digital Converter with 204ns Dynamic Range For Time-resolved Imaging and Ranging Applications

Time-resolved quantization has become inherent in systems that incorporate a Time-of-Flight (ToF) or Time-of-Arrival (ToA) measurement. Such systems have diverse applications ranging from direct time-of-flight measurements in 3D ranging systems such as Radar and Lidar systems to imaging systems using Time-Correlated Single Photon Counting (TCSPC) (in fields such as nuclear instrumentation, molecular biology, artificial vision in computer systems, etc.). Time resolution in the order of picoseconds, especially in imaging applications has become important due to the increasing demands on the functionality and accuracy of the DSP (digital signal processing) in such systems. The increasing density of integration in CMOS implementations of such imaging and ranging systems places large constrains on area and power consumption. Furthermore, the increased variability of the range of the measurement quantities introduces an undesirable trade-off between dynamic range and precision/resolution. Therefore there is a need for time-to-digital converters which achieve high precision, high resolution and large dynamic range, without excessive costs in area and power. In this thesis, a wide range, high resolution TDC is designed to offer a timing resolution of less than 10ps and a dynamic range of 204.8ns. This is achieved by using a digitally-intensive hierarchical approach, using two looped structures, which incorporates a novel control logic algorithm. This guarantees accurate operation of the loops, removing the possibility of MSB errors in the digital word. Firstly the measurement is subdivided into 2 different sections: a coarse quantization and a fine quantization. Both of the conversion steps involve the use of a looped delay–line structure utilizing only 4 elements per delay line. This together with the control logic, makes the design of a wide dynamic range TDC achievable without excessive area and power consumption. The design has been simulated, fabricated and tested in the IBM 0.18μm technology. The proposed design achieves a resolution of 8.125ps with an input dynamic range of 204.8ns, a maximum input occurrence rate of 100MHz and a minimum dead time of 7.5ns. The fabricated TDC has a power consumption of < 20mW (1.8V supply; FSR signal at 4MS/s) and < 35mW at the maximum output rate of 100MS/s

An On-chip PVT Resilient Short Time Measurement Technique

As the CMOS technology nodes continue to shrink, the challenges of developing manufacturing tests for integrated circuits become more difficult to address. To detect parametric faults of new generation of integrated circuits such as 3D ICs, on-chip short-time intervals have to be accurately measured. The accuracy of an on-chip time measurement module is heavily affected by Process, supply Voltage, and Temperature (PVT) variations. This work presents a new on-chip time measurement scheme where the undesired effects of PVT variations are attenuated significantly. To overcome the effects of PVT variations on short-time measurement, phase locking methodology is utilized to implement a robust Vernier delay line. A prototype Time-to-Digital Converter (TDC) has been fabricated using TSMC 0.180 µm CMOS technology and experimental measurements have been carried out to verify the performance parameters of the TDC. The measurement results indicate that the proposed solution reduces the effects of PVT variations by more than tenfold compared to a conventional on-chip TDC. A coarse-fine time interval measurement scheme which is resilient to the PVT variations is also proposed. In this approach, two Delay Locked Loops (DLLs) are utilized to minimize the effects of PVT on the measured time intervals. The proposed scheme has been implemented using CMOS 65nm technology. Simulation results using Advanced Design System (ADS) indicate that the measurement resolution varies by less than 0.1ps with ±15% variations of the supply voltage. The proposed method also presents a robust performance against process and temperature variations. The measurement accuracy changes by a maximum of 0.05ps from slow to fast corners. The implemented TDC presents a robust performance against temperature variations too and its measurement accuracy varies a few femto-seconds from -40 ºC to +100 ºC. The principle of robust short-time measurement was used in practice to design and implement a state-of-the-art Coordinate Measuring Machine (CMM) for an industry partner to measure geometrical features of transmission parts with micrometer resolution. The solution developed for the industry partner has resulted in a patent and a product in the market. The on-chip short-time measurement technology has also been utilized to develop a solution to detect Hardware Trojans

NASA Tech Briefs Index 1978

Tech Briefs are short announcements of new technology derived from the research and development activities of the National Aeronautics and Space Administration. These briefs emphasize information considered likely to be transferrable across industrial, regional, or disciplinary lines and are issued to encourage commercial application. This Index to NASA Tech Briefs contains abstracts and four indexes -- subject, personal author, originating Center, and Tech Brief number -- for 1978 Tech Briefs

Publications of the Jet Propulsion Laboratory 1987

A bibliography is presented which describes and indexes by author the externally distributed technical reporting, released during the calender year 1987, that resulted from scientific and engineering work performed, or managed, by the Jet Propulsion Lab. Three classes of publications are included: (1) JPL publications in which the information is complete for a specific accomplishment; (2) Articles from the quarterly Telecommunications and Data Acquisition Progress Report; and (3) Articles published in the open literature

Quadrature Phase-Domain ADPLL with Integrated On-line Amplitude Locked Loop Calibration for 5G Multi-band Applications

5th generation wireless systems (5G) have expanded frequency band coverage with the low-band 5G and mid-band 5G frequencies spanning 600 MHz to 4 GHz spectrum. This dissertation focuses on a microelectronic implementation of CMOS 65 nm design of an All-Digital Phase Lock Loop (ADPLL), which is a critical component for advanced 5G wireless transceivers. The ADPLL is designed to operate in the frequency bands of 600MHz-930MHz, 2.4GHz-2.8GHz and 3.4GHz-4.2GHz. Unique ADPLL sub-components include: 1) Digital Phase Frequency Detector, 2) Digital Loop Filter, 3) Channel Bank Select Circuit, and 4) Digital Control Oscillator. Integrated with the ADPLL is a 90-degree active RC-CR phase shifter with on-line amplitude locked loop (ALL) calibration to facilitate enhanced image rejection while mitigating the effects of fabrication process variations and component mismatch. A unique high-sensitivity high-speed dynamic voltage comparator is included as a key component of the active phase shifter/ALL calibration subsystem. 65nm CMOS technology circuit designs are included for the ADPLL and active phase shifter with simulation performance assessments. Phase noise results for 1 MHz offset with carrier frequencies of 600MHz, 2.4GHz, and 3.8GHz are -130, -122, and -116 dBc/Hz, respectively. Monte Carlo simulations to account for process variations/component mismatch show that the active phase shifter with ALL calibration maintains accurate quadrature phase outputs when operating within the frequency bands 600MHz-930MHz, 2.4GHz-2.8GHz and 3.4GHz-4.2GHz