322 research outputs found
Research in the effective implementation of guidance computers with large scale arrays Interim report
Functional logic character implementation in breadboard design of NASA modular compute
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Behavioral synthesis from VHDL using structured modeling
This dissertation describes work in behavioral synthesis involving the development of a VHDL Synthesis System VSS which accepts a VHDL behavioral input specification and performs technology independent synthesis to generate a circuit netlist of generic components. The VHDL language is used for input and output descriptions. An intermediate representation which incorporates signal typing and component attributes simplifies compilation and facilitates design optimization.A Structured Modeling methodology has been developed to suggest standard VHDL modeling practices for synthesis. Structured modeling provides recommendations for the use of available VHDL description styles so that optimal designs will be synthesized.A design composed of generic components is synthesized from the input description through a process of Graph Compilation, Graph Criticism, and Design Compilation. Experiments were performed to demonstrate the effects of different modeling styles on the quality of the design produced by VSS. Several alternative VHDL models were examined for each benchmark, illustrating the improvements in design quality achieved when Structured Modeling guidelines were followed
SLIM: A Language for Microcode Description and Simulation in VLSI
SLIM (Stanford Language for Implementing Microcode) is a programming language based system for
specifying and simulating microcode in a VLSI chip. The language is oriented towards PLA
implementations of microcoded machines using either a microprogram counter or a finite state
machine. The system supports simulation of the microcode and will drive a PLA layout program to
automatically create the PLA
HAL-ASOS accelerator model: evolutive elasticity by design
To address the integration of software threads and hardware accelerators into the Linux Operating System (OS) programming models, an accelerator architecture is proposed, based on micro-programmable hardware system calls, which fully export these resources into the Linux OS user-space through a design-specific virtual file system. The proposed HAL-ASOS accelerator model is split into a user-defined Hardware Task and a parameterizable Hardware Kernel with three differentiated transfer channels, aiming to explore distinct BUS technology interfaces and promote the accelerator to a first-class computing unit. This paper focuses on the Hardware Kernel and mainly its microcode control unit, which will leverage the elasticity to naturally evolve with Linux OS through key differentiating capabilities of field programmable gate arrays (FPGAs) when compared to the state of the art. To comply with the evolutive nature of Linux OS, or any Hardware Task incremental features, the proposed model generates page-faults signaling runtime errors that are handled at the kernel level as part of the virtual file system runtime. To evaluate the accelerator model’s programmability and its performance, a client-side application based on the AES 128-bit algorithm was implemented. Experiments demonstrate a flexible design approach in terms of hardware and software reconfiguration and significant performance increases consistent with rising processing demands or clock design frequencies.This work has been supported by FCT-Fundação para a Ciência e Tecnologia within the R&D Units Project Scope: UIDB/00319/2020
The formal verification of generic interpreters
The task assignment 3 of the design and validation of digital flight control systems suitable for fly-by-wire applications is studied. Task 3 is associated with formal verification of embedded systems. In particular, results are presented that provide a methodological approach to microprocessor verification. A hierarchical decomposition strategy for specifying microprocessors is also presented. A theory of generic interpreters is presented that can be used to model microprocessor behavior. The generic interpreter theory abstracts away the details of instruction functionality, leaving a general model of what an interpreter does
Techniques for the realization of ultrareliable spaceborne computers Interim scientific report
Error-free ultrareliable spaceborne computer
A heterogeneous computer vision architecture: implementation issues
The prototype of a heterogeneous architecture is currently being built. The architecture is aimed at video-rate computing and is based on a message passing MIMD topology at the top level-transputer based-and on VLSI associative processor arrays (APA, SIMD structure) for low level image processing tasks. The APA structure is implemented through a set of 4 VLSI chips (GLiTCH) containing 64 1-bit processing elements each. This communication addresses some issues concerning the implementation of the first prototype, namely those related to:
• the design and integration of the APA controller unit, which provides the required interface between the APA, the MIMD topology and the video image interface:
• the evaluation of the GLiTCH chip through an emulator based on transputers and fast programmable devices; the emulator was designed to be flexible enough to evaluate later modifications to the GLiTCH design;
• the design of an integrated set of software development tools containing a structured editor-syntax oriented, with a visual interface/programming interface-and a cross compiler and debugger
HAL-ASOS - Linux com aceleração em hardware para sistemas operativos dedicados à aplicação
Programa doutoral em Engenharia Eletrónica e de Computadores (PDEEC) (especialidade de Informática Industrial e Sistemas Embebidos)O ecossistema de sistemas embebidos de hoje tornou-se enorme, cobrindo vários e diferentes sistemas,
exigindo desempenho e mobilidade completa enquanto atingem autonomias de bateria cada vez maiores.
Mas a crescente frequência de relógio que resultou em dispositivos cada vez mais rápidos começou a
estagnar antes dos transístores pararem de encolher. Plataformas Field Programmable Gate Array (FPGA)
são uma solução alternativa para a implementação de sistemas completos e reconfiguráveis. Fornecem
desempenho e eficiência computacional para satisfazer requisitos da aplicação e do sistema embebido.
Vários Sistemas Operativos (SO) assistidos por FPGA foram propostos, mas ao estreitar seu foco na síntese
do datapath do acelerador de hardware, a grande maioria ignora a integração semântica destes no
SO. Ambientes de síntese de alto nível (HLS) elevaram a abstração além da linguagem de transferência de
registo (RTL), seguindo uma abordagem específica de domínio enquanto misturam software e abstrações
de hardware ad hoc, que dificultam as otimizações. Além disso, os modelos de programação para software
e hardware reconfigurável carecem de semelhanças, o que com o tempo dificultará a Exploração
do Ambiente de Design (DSE) e diminuirá o potencial de reutilização de código. Para responder a estas
necessidades, propomos HAL-ASOS, uma ferramenta para implementar sistemas embebidos baseados
em Linux que fornece (1) elasticidade no design em conformidade com a natureza evolutiva deste SO, (2)
integração semântica profunda de tarefas de hardware nos modelos de programação do Linux, (3) facilidade
na gestão de complexidade através de metodologia e ferramentas para apoiar o design, verificação
e implementação, (4) orientada por princípios de design híbridos e eficiência no sistema. Para avaliar as
funcionalidades da ferramenta, foi implementado um aplicativo criptográfico que demonstra alcance de
desempenho enquanto se emprega a metodologia de design. Novos níveis de desempenho são atingidos
numa aplicação de Visão por Computador que explora recursos de programação assíncrona-síncrona. Os
resultados demonstram uma abordagem flexível na reconfiguração entre hardware e software, e desempenho
que aumenta consistentemente com acréscimo de recursos ou frequência de relógio.Today’s embedded systems ecosystem became huge while covering several and different computer-based
systems, demanding for performance and complete mobility while experiencing longer battery lives. But
the rampant frequency that resulted in faster devices began hitting a wall even before transistors stopped
shrinking. Field Programmable Gate Array (FPGA) platforms are an alternative solution towards implementing
complete reconfigurable systems. They provide computational power, efficiency, in a lightweight
solution to serve the application requirements and increase performance in the overall system. Several
FPGA-assisted Operating Systems (OS) have been proposed, but by narrowing their focus on datapath
synthesis of the hardware accelerator, they completely ignore the deep semantic integration of these accelerators
into the OS. State-of-the-art High-Level Synthesis (HLS) environments have raised the level of
abstraction beyond Register Transfer Language (RTL) by following a domain-specific approach while mixing
ad hoc software and hardware abstractions, making harder for performance optimizations. Furthermore,
the programming models for software and reconfigurable hardware lack commonalities, which in time will
hinder the Design Space Exploration (DSE) and lower the potential for code reuse. To overcome these
issues, we propose HAL-ASOS, a framework to implement Linux-based Embedded systems which provides
(1) elasticity by design to comply with the evolutive nature of Linux, (2) deep semantic integration of the
hardware tasks in the Linux programming models, (3) easy complexity management using methodology
and tools to fully support design, verification and deployment, (4) hybrid and efficiency-oriented design
principles. To evaluate the framework functionalities, a cryptographic application was implemented and
demonstrates performance achievements while using the promoted application-driven design methodology.
To demonstrate new levels of performance that can be achieved, a Computer Vision application
explores several mixed asynchronous-synchronous programming features. Experiments demonstrate a
flexible design approach in terms of hardware and software reconfiguration, and significant performance
that increases consistently with the rising in processing resources or clock frequencies.Financial support received from Portuguese Foundation for Science and Technology (FCT) with the PhD grant SFRH/BD/82732/2011
Timing Architecture for ESS
Programa Oficial de Doutoramento en Investigación en Tecnoloxías da Información. 5023V01[Resumo]
O sistema de temporización é unha compoñente fundamental para o control e sincronización de
instalacións industriais e científicas, coma aceleradores de partículas. Nesta tese
traballamos na especificación e desenvolvemento do sistema de temporización para a European
Spallation Source (ESS), a maior fonte de neutróns actualmente en construción. Abordamos
este tra ballo a dous niveis: a especificación do sistema de temporización, e a imple mentación
física de sistemas de control empregando circuítos reconfigurables.
Con respecto á especificación do sistema de temporización, deseñamos e implementamos a
configuración do protocolo de temporización para cumprir cos requirimentos do ESS e ideamos un modo
de operación e unha aplicación para a configuración e control do sistema de temporización.
Tamén presentamos unha ferramenta e unha metodoloxía para imple mentar sistemas de
control empregando FPGAs, coma os nodos do sistema de temporización. ámbalas <lúas están baseadas
en statecharts, unha repre sentación gráfica de sistemas que expande o concepto de máquinas de
estados finitos, orientada a sistemas que necesitan ser reconfigurados rápidamente en múltiples
localizacións minimizando a posibilidade de erros. A ferramenta crea automaticamente código
VHDL sintetizable a partir do statechart do sistema. A metodoloxía explica o procedemento
para implementar o state chart como unha arquitectura microprogramada en FPGAs.[Resumen]
El sistema de temporización es un componente fundamental para el control y sincronización de
instalaciones industriales y científicas, como aceleradores e partículas. En esta tesis
trabajamos en la especificación y desarrollo el sistema de temporización para la European
Spallation Source (ESS), la mayor fuente de neutrones actualmente en construcción.
Abordamos este trabajo en dos niveles: la especificación del sistema de temporización, y la
mplementación física de sistemas de control empleando circuitos reconfig rables.
Con respecto a la especificación del sistema de temporización, diseñamos
e implementamos la configuración del protocolo de temporización para cumplir on los requisitos de
ESS e ideamos un modo de operación y una aplicación ara la configuración y control del sistema
de temporización.
También presentamos una herramienta y una metodología para imple entar sistemas de control
empleando FPGAs, como los nodos del sistema e temporización. Ambas están basadas en statecharts)
una representación gráfica de sistemas que expande el concepto de máquinas de estados
fini os, orientada a sistemas que necesitan ser reconfigurados rápidamente en últiples
localizaciones minimizando la posibilidad de errores. La herramienta crea
automáticamente código VHDL sintetizable a partir del statechart del sistema. La metodología
explica el procedimiento para implementar el statechart como una arquitectura microprogramada en FPGAs.[Abstract]
The timing system is a key component for the control and synchronization of industrial and
scientific facilities, such as particle accelerators. In this thesis we tackle the
specification and development of the timing system for the European Spallation Source (ESS), the
largest neutron source currently in construction. We approach this work at two levels:
the specification of the timing system and the physical implementation of control systems using
reconfigurable hardware.
Regarding the specification of the timing system, we designed and imple mented the configuration
of the timing protocol to fulfil the requirements of ESS and devised an operation mode andan
application for the configuration and control of the timing system.
We also present one too! and one methodology to implement control systems using FPGAs,
such as the nodes of the timing system. Both are based on statecharts, a graphical
representation of systems that expand the concepts of Finite State Machines, targeted at
systems that need to be re configured quickly in multiple locations minimizing the
chance of errors. The too! automatically creates synthesizable VHDL code from a statechart of
the system. The methodology explains the procedure to implement the statechart as a
microprogrammed architecture in FPGAs
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