A Low-Power DSP Architecture for a Fully Implantable Cochlear Implant System-on-a-Chip.

The National Science Foundation Wireless Integrated Microsystems (WIMS) Engineering Research Center at the University of Michigan developed Systems-on-a-Chip to achieve biomedical implant and environmental monitoring functionality in low-milliwatt power consumption and 1-2 cm3 volume. The focus of this work is implantable electronics for cochlear implants (CIs), surgically implanted devices that utilize existing nerve connections between the brain and inner-ear in cases where degradation of the sensory hair cells in the cochlea has occurred. In the absence of functioning hair cells, a CI processes sound information and stimulates the nderlying nerve cells with currents from implanted electrodes, enabling the patient to understand speech. As the brain of the WIMS CI, the WIMS microcontroller unit (MCU) delivers the communication, signal processing, and storage capabilities required to satisfy the aggressive goals set forth. The 16-bit MCU implements a custom instruction set architecture focusing on power-efficient execution by providing separate data and address register windows, multi-word arithmetic, eight addressing modes, and interrupt and subroutine support. Along with 32KB of on-chip SRAM, a low-power 512-byte scratchpad memory is utilized by the WIMS custom compiler to obtain an average of 18% energy savings across benchmarks. A synthesizable dynamic frequency scaling circuit allows the chip to select a precision on-chip LC or ring oscillator, and perform clock scaling to minimize power dissipation; it provides glitch-free, software-controlled frequency shifting in 100ns, and dissipates only 480μW. A highly flexible and expandable 16-channel Continuous Interleaved Sampling Digital Signal Processor (DSP) is included as an MCU peripheral component. Modes are included to process data, stimulate through electrodes, and allow experimental stimulation or processing. The entire WIMS MCU occupies 9.18mm2 and consumes only 1.79mW from 1.2V in DSP mode. This is the lowest reported consumption for a cochlear DSP. Design methodologies were analyzed and a new top-down design flow is presented that encourages hardware and software co-design as well as cross-domain verification early in the design process. An O(n) technique for energy-per-instruction estimations both pre- and post-silicon is presented that achieves less than 4% error across benchmarks. This dissertation advances low-power system design while providing an improvement in hearing recovery devices.Ph.D.Electrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/91488/1/emarsman_1.pd

Design of a Control System for a Micro Power Plant

Si analizza una rete di piccola potenza e nel dettaglio si cerca di massimizzare il flusso di potenza così da sfruttare la rete nel miglior modo possibile. La prima parte del lavoro si concentra su uno studio tramite simulazioni al computer grazie a MATLAB/SIMULINK mentre la seconda parte riguarda la realizzazione fisica di impulsi PWM da fornire all'inverter per ottenere la forma d'onda sinusoidale fondamentale della tension

Ordinateur de bord pour mini satellite

Objectif Développement d’une nouvelle carte électronique pour le sous-système CDMS (Control & Data Management System) du satellite Swisscube, sur la base des résultats de tests du modèle prototype. Ce picosatellite développé entièrement par des étudiants de différentes hautes écoles de Suisse, sera lancé vers la fin de l’année 2008. Résultats Le modèle de qualification du CDMS a été développé et testé. Ces différents tests ont permis de démontrer le bon fonctionnent de la carte pour les différentes fonctionnalités et spécifications requises. La carte du CDMS est entièrement opérationnelle et peu être transmise au team responsable du développement software du CDMS, pour effectuer leurs tests d’intégration. Mots-clés CDMS, CubeSat, Swisscube, microcontrôleur, mémoires, I2C, SPI, OpenOCD, JTAGkey, EclipseZiel Entwurf einer neuen elektronischen Karte für das Subsystem CDMS des Swisscube Satelliten, welche auf die Resultate von Tests des Prototypenmodells basiert ist. Dieser Picosatellit, welcher von Schweizer Fachhochstudenten entwickelt worden ist, wird Ende 2008 gestartet. Resultate Das Qualifikationsmodell des CDMS wurde entwickelt und getestet. Diese Tests erlaubten es, das gute Funktionieren der verschiedenen erforderlichen Funktionalitäten und Spezifizierungen zu beweisen. Die CDMS Karte ist einsatzfähig und kann dem verantwortlichen Team der Entwicklung der CDM -Software weitergeleitet werden, um die Integrationsteste durchzuführen. Schlüsselwörter CDMS, CubeSat, Swisscube, Mikrokontroller, Speicher, I2C, SPI, OpenOCD, JTAGkey, Eclips

Design and analysis of SRAMs for energy harvesting systems

PhD ThesisAt present, the battery is employed as a power source for wide varieties of microelectronic systems ranging from biomedical implants and sensor net-works to portable devices. However, the battery has several limitations and incurs many challenges for the majority of these systems. For instance, the design considerations of implantable devices concern about the battery from two aspects, the toxic materials it contains and its lifetime since replacing the battery means a surgical operation. Another challenge appears in wire-less sensor networks, where hundreds or thousands of nodes are scattered around the monitored environment and the battery of each node should be maintained and replaced regularly, nonetheless, the batteries in these nodes do not all run out at the same time. Since the introduction of portable systems, the area of low power designs has witnessed extensive research, driven by the industrial needs, towards the aim of extending the lives of batteries. Coincidentally, the continuing innovations in the field of micro-generators made their outputs in the same range of several portable applications. This overlap creates a clear oppor-tunity to develop new generations of electronic systems that can be powered, or at least augmented, by energy harvesters. Such self-powered systems benefit applications where maintaining and replacing batteries are impossi-ble, inconvenient, costly, or hazardous, in addition to decreasing the adverse effects the battery has on the environment. The main goal of this research study is to investigate energy harvesting aware design techniques for computational logic in order to enable the capa- II bility of working under non-deterministic energy sources. As a case study, the research concentrates on a vital part of all computational loads, SRAM, which occupies more than 90% of the chip area according to the ITRS re-ports. Essentially, this research conducted experiments to find out the design met-ric of an SRAM that is the most vulnerable to unpredictable energy sources, which has been confirmed to be the timing. Accordingly, the study proposed a truly self-timed SRAM that is realized based on complete handshaking protocols in the 6T bit-cell regulated by a fully Speed Independent (SI) tim-ing circuitry. The study proved the functionality of the proposed design in real silicon. Finally, the project enhanced other performance metrics of the self-timed SRAM concentrating on the bit-line length and the minimum operational voltage by employing several additional design techniques.Umm Al-Qura University, the Ministry of Higher Education in the Kingdom of Saudi Arabia, and the Saudi Cultural Burea

General-Purpose Digital Filter Platform

This senior project provides a platform for high-speed, general-purpose digital filter implementation. EE 459 currently implements digital filters using reprogrammable digital signal processor boards. These aging digital signal processors serially calculate each difference equation term. Operating at 1 Mega-sample per second, the new general-purpose platform simultaneously processes at least ten digital filtering difference equation coefficients. The platform also features an audio jack input and BNC connectors for viewing input and output signals. The filter digitizes single channel audio signals at 44.1 kHz sampling rate with 16-bit precision or 1 MHz sampling at 8-bit precision. The new reprogrammable platform includes a data acquisition computer interface. This general-purpose digital filter supports a more modern approach to DSP development than the current platform

Brain Controlled Switch

This study aims at designing and implementing a single channel stand-alone Brain-Controlled Switch (BCS) device, which records the electroencephalography (EEG) signals from the scalp using electrodes, amplifies it, eliminates interferences (associated with the EEG signals) and processes the EEG signals to extract and decode temporal signal features to determine user’s intention of regulating an external switch. The design of our “brain-controlled switch” device is implemented using a bio-potential amplifier and a microcontroller. The bio-potential amplifier amplifies the EEG signals to a level sufficient for processing, eliminates interferences and ensures patient safety. The microcontroller (dsPIC30F4013) digitizes the amplified and conditioned analog EEG signals from the bio-potential amplifier, extracts the desired signal features for decoding and prediction of user’s intention and accordingly operates the external switch. When the user concentrates on an external visual stimulus or performs externally triggered movement (hand movement or motor imagery movement), a reproducible pattern appears in user’s EEG frequency bands. The analysis of these patterns is used to decode and predict user’s intention to operate an external switch. To realize our “brain-controlled switch”, we explored two EEG sources: steady-state visually evoked potentials (SSVEP) and beta rebounds, which are patterns generated in the EEG frequency bands associated with focusing on an external visual stimulus or performing externally triggered movements. In case of SSVEP based brain controlled switch, a repetitive visual stimulus (LED flickering at a specified frequency) was used. When the user concentrates on the flickering LED, a dominant fundamental frequency (equivalent to the flickering frequency) appears in the spectral representation of the EEG signals recorded at occipital lobes. Our microcontroller implemented a digital band pass filter to extract the frequency band containing this fundamental frequency and continuously took an average of the amplitude power every predetermined time interval. Whenever the amplitude average power exceeded the preset power threshold the external switch was turned ON. A healthy subject participated in this study, and it took approximately 3.14 ± 1.81 seconds of active concentration for the subject to turn ON the switch in real time with a false positive rate of 1.17%. In case of beta rebound based brain controlled switch, the subject was instructed to perform a brisk hand movement following an external synchronization signal. Our design focused on the post-movement beta rebound which occurs after the cessation of the movement to operate the external switch. Our microcontroller in this case implemented a digital band pass filter to extract the beta band and continuously took an average of its amplitude power every predetermined time interval. Whenever the amplitude average power exceeded the preset power threshold the external switch was turned ON. It took approximately 12.23 ± 7.39 seconds of active urging time by the subject to turn ON the switch in real time with a false positive rate of 9.33%. Thus we have designed a novel stand-alone BCS device which operates an external switch by decoding and predicting user’s intentions

DIEstro: Motion sensor platform for cattle oestrus detection

The reproductive efficiency of dairy industry has decreased over the last ten years due mainly to an intensification of the management techniques of the herd, and an increase of total number of animals. A main objective of worldwide dairy farms is to ensure that dairy cows, produce as much milk as possible. A cow produces milk while it has a calf to breastfeed, therefore, the less time passes between births, the more ”productive” the cows are. This is the principal reason why the precise heat (oestrus) detection has became so important, a task traditionally assigned to veterinary and expert people examining and watching the cattle behavior, and in recent years to electronic devices monitoring the cow’s physical activity. Tracking the animal’s physical activity by means of a portable device strapped to each animal, is known to be a very effective way to determine heat, but sometimes requires expensive hardware and large batteries. In this work, a low-cost micropower wireless system able to automatically detect oestrus period of cattle is presented. It was designed in cooperation with BQN, a company developing technology for the agribusiness industry in Uruguay. The tracker seizes the recent availability of 1 uA micropower accelerometers, LoRa long range transceivers, and FRAM microcontrollers, to achieve a coin cell battery powered paradigm for oestrus detection. The device records 3 axis acceleration information, process it, and periodically sends it to a server; it has a measured ultra low power consumption of 4 uA while collecting/processing data, reaching a very large (> 10km) communication distance using a star topology and LoRa technology at countryside areas. The scope of the project and this documentation is the entire hardware and firmware development, from the start idea, design and final implementation.Agencia Nacional de Investigación e Innovació

Low Power Circuits for Smart Flexible ECG Sensors

Cardiovascular diseases (CVDs) are the world leading cause of death. In-home heart condition monitoring effectively reduced the CVD patient hospitalization rate. Flexible electrocardiogram (ECG) sensor provides an affordable, convenient and comfortable in-home monitoring solution. The three critical building blocks of the ECG sensor i.e., analog frontend (AFE), QRS detector, and cardiac arrhythmia classifier (CAC), are studied in this research. A fully differential difference amplifier (FDDA) based AFE that employs DC-coupled input stage increases the input impedance and improves CMRR. A parasitic capacitor reuse technique is proposed to improve the noise/area efficiency and CMRR. An on-body DC bias scheme is introduced to deal with the input DC offset. Implemented in 0.35m CMOS process with an area of 0.405mm2, the proposed AFE consumes 0.9W at 1.8V and shows excellent noise effective factor of 2.55, and CMRR of 76dB. Experiment shows the proposed AFE not only picks up clean ECG signal with electrodes placed as close as 2cm under both resting and walking conditions, but also obtains the distinct -wave after eye blink from EEG recording. A personalized QRS detection algorithm is proposed to achieve an average positive prediction rate of 99.39% and sensitivity rate of 99.21%. The user-specific template avoids the complicate models and parameters used in existing algorithms while covers most situations for practical applications. The detection is based on the comparison of the correlation coefficient of the user-specific template with the ECG segment under detection. The proposed one-target clustering reduced the required loops. A continuous-in-time discrete-in-amplitude (CTDA) artificial neural network (ANN) based CAC is proposed for the smart ECG sensor. The proposed CAC achieves over 98% classification accuracy for 4 types of beats defined by AAMI (Association for the Advancement of Medical Instrumentation). The CTDA scheme significantly reduces the input sample numbers and simplifies the sample representation to one bit. Thus, the number of arithmetic operations and the ANN structure are greatly simplified. The proposed CAC is verified by FPGA and implemented in 0.18m CMOS process. Simulation results show it can operate at clock frequencies from 10KHz to 50MHz. Average power for the patient with 75bpm heart rate is 13.34W

The 1991 3rd NASA Symposium on VLSI Design

Papers from the symposium are presented from the following sessions: (1) featured presentations 1; (2) very large scale integration (VLSI) circuit design; (3) VLSI architecture 1; (4) featured presentations 2; (5) neural networks; (6) VLSI architectures 2; (7) featured presentations 3; (8) verification 1; (9) analog design; (10) verification 2; (11) design innovations 1; (12) asynchronous design; and (13) design innovations 2