Low power, compact charge coupled device signal processing system

A variety of charged coupled devices (CCDs) for performing programmable correlation for preprocessing environmental sensor data preparatory to its transmission to the ground were developed. A total of two separate ICs were developed and a third was evaluated. The first IC was a CCD chirp z transform IC capable of performing a 32 point DFT at frequencies to 1 MHz. All on chip circuitry operated as designed with the exception of the limited dynamic range caused by a fixed pattern noise due to interactions between the digital and analog circuits. The second IC developed was a 64 stage CCD analog/analog correlator for performing time domain correlation. Multiplier errors were found to be less than 1 percent at designed signal levels and less than 0.3 percent at the measured smaller levels. A prototype IC for performing time domain correlation was also evaluated

A Low-Power and High-Speed Frequency Multiplier for DLL-Based Clock Generator

A low-power and high-speed frequency multiplier for a delay-locked loop-based clock generator is proposed to generate a multiplied clock with different range of frequencies. The modified edge combiner consumes low power and achieves a high-speed operation. The proposed frequency multiplier overcomes a deterministic jitter problem by reducing the delay difference between positive- and negative-edge generation paths. The proposed frequency multiplier is implemented in a 0.13-µm CMOS process technology achieved power consumption to a frequency ratio of 2.9 µW/MHz, and has the multiplication ratios of 16, and an output range of 100 MHz–3.3 GHz

A Low Phase Noise All-Digital Programmable DLL-Based Clock Generator

[[abstract]]This paper proposes a low phase noise all-digital programmable DLL-based clock generator. The proposed clock generator is fabricated in a 0.18 μm standard CMOS process with a 1.8 V supply voltage. The proposed digital programmable DLL-based clock generator is easy migration over different processes and low power dissipation. The measurement results show that the input and output frequency ranges can operate 100 MHz ~ 600 MHz and 100 MHz ~ 1.2 GHz, respectively. At 800 MHz, the phase noise is -112.36 dBc @ 1MHz offset frequency. The total power consumption of the clock generator is 23.87 mW, and the active die area of the clock generator is 0.14 mm2.[[conferencetype]]國際[[conferencedate]]20140426~20140428[[booktype]]電子版[[iscallforpapers]]Y[[conferencelocation]]Sapporo, Japa

The S2 VLBI Correlator: A Correlator for Space VLBI and Geodetic Signal Processing

We describe the design of a correlator system for ground and space-based VLBI. The correlator contains unique signal processing functions: flexible LO frequency switching for bandwidth synthesis; 1 ms dump intervals, multi-rate digital signal-processing techniques to allow correlation of signals at different sample rates; and a digital filter for very high resolution cross-power spectra. It also includes autocorrelation, tone extraction, pulsar gating, signal-statistics accumulation.Comment: 44 pages, 13 figure

High-resolution wide-band Fast Fourier Transform spectrometers

We describe the performance of our latest generations of sensitive wide-band high-resolution digital Fast Fourier Transform Spectrometer (FFTS). Their design, optimized for a wide range of radio astronomical applications, is presented. Developed for operation with the GREAT far infrared heterodyne spectrometer on-board SOFIA, the eXtended bandwidth FFTS (XFFTS) offers a high instantaneous bandwidth of 2.5 GHz with 88.5 kHz spectral resolution and has been in routine operation during SOFIA's Basic Science since July 2011. We discuss the advanced field programmable gate array (FPGA) signal processing pipeline, with an optimized multi-tap polyphase filter bank algorithm that provides a nearly loss-less time-to-frequency data conversion with significantly reduced frequency scallop and fast sidelobe fall-off. Our digital spectrometers have been proven to be extremely reliable and robust, even under the harsh environmental conditions of an airborne observatory, with Allan-variance stability times of several 1000 seconds. An enhancement of the present 2.5 GHz XFFTS will duplicate the number of spectral channels (64k), offering spectroscopy with even better resolution during Cycle 1 observations.Comment: Accepted for publication in A&A (SOFIA/GREAT special issue

Digital frequency synthesizer for radar astronomy

The digital frequency synthesizer (DFS) is an integral part of the programmable local oscillator (PLO) which is being developed for the NASA's Deep Space Network (DSN) and radar astronomy. Here, the theory of operation and the design of the DFS are discussed, and the design parameters in application for the Goldstone Solar System Radar (GSSR) are specified. The spectral purity of the DFS is evaluated by analytically evaluating the output spectrum of the DFS. A novel architecture is proposed for the design of the DFS with a frequency resolution of 1/2(exp 48) of the clock frequency (0.35 mu Hz at 100 MHz), a phase resolution of 0.0056 degrees (16 bits), and a frequency spur attenuation of -96 dBc

A Scalable Correlator Architecture Based on Modular FPGA Hardware, Reuseable Gateware, and Data Packetization

A new generation of radio telescopes is achieving unprecedented levels of sensitivity and resolution, as well as increased agility and field-of-view, by employing high-performance digital signal processing hardware to phase and correlate large numbers of antennas. The computational demands of these imaging systems scale in proportion to BMN^2, where B is the signal bandwidth, M is the number of independent beams, and N is the number of antennas. The specifications of many new arrays lead to demands in excess of tens of PetaOps per second. To meet this challenge, we have developed a general purpose correlator architecture using standard 10-Gbit Ethernet switches to pass data between flexible hardware modules containing Field Programmable Gate Array (FPGA) chips. These chips are programmed using open-source signal processing libraries we have developed to be flexible, scalable, and chip-independent. This work reduces the time and cost of implementing a wide range of signal processing systems, with correlators foremost among them,and facilitates upgrading to new generations of processing technology. We present several correlator deployments, including a 16-antenna, 200-MHz bandwidth, 4-bit, full Stokes parameter application deployed on the Precision Array for Probing the Epoch of Reionization.Comment: Accepted to Publications of the Astronomy Society of the Pacific. 31 pages. v2: corrected typo, v3: corrected Fig. 1

FPGA Implementation of Spectral Subtraction for In-Car Speech Enhancement and Recognition

The use of speech recognition in noisy environments requires the use of speech enhancement algorithms in order to improve recognition performance. Deploying these enhancement techniques requires significant engineering to ensure algorithms are realisable in electronic hardware. This paper describes the design decisions and process to port the popular spectral subtraction algorithm to a Virtex-4 field-programmable gate array (FPGA) device. Resource analysis shows the final design uses only 13% of the total available FPGA resources. Waveforms and spectrograms presented support the validity of the proposed FPGA design

Customisable arithmetic hardware designs

Imperial Users onl

A synchronised Direct Digital Synthesiser

We describe a Direct Digital Synthesiser (DDS) which provides three frequency-locked synchronised outputs to generate frequencies from DC to 160 MHz. Primarily designed for use in a heterodyning range imaging system, the flexibility of the design allows its use in a number of other applications which require any number of stable, synchronised high frequency outputs. Frequency tuning of 32 bit length provides 0.1 Hz resolution when operating at the maximum clock rate of 400 MSPS, while 14 bit phase tuning provides 0.4 mrad resolution. The DDS technique provides very high relative accuracy between outputs, while the onboard oscillator’s stability of ±1 ppm adds absolute accuracy to the design