Design of a ROIC for scanning type HgCdTe LWIR focal plane arrays

Design of a silicon readout integrated circuit (ROIC) for LWIR HgCdTe Focal Plane is presented. ROIC incorporates time delay integration (TDI) functionality over seven elements with a supersampling rate of three, increasing SNR and the spatial resolution. Novelty of this topology is inside TDI stage; integration of charges in TDI stage implemented in current domain by using switched current structures that reduces required area for chip and improves linearity performance. ROIC, in terms of functionality, is capable of bidirectional scan, programmable integration time and 5 gain settings at the input. Programming can be done parallel or serially with digital interface. ROIC can handle up to 3.5V dynamic range with the input stage to be direct injection (DI) type. With the load being 10pF capacitive in parallel with 1MΩ resistance, output settling time is less than 250nsec enabling the clock frequency up to 4MHz. The manufacturing technology is 0.35μm, double poly-Si, four-metal (3 metals and 1 top metal) 5V CMOS process

Realization of low power, highly linear roic with current mode TDI for long wave infrared detectors

Infrared (IR) imaging systems can be used for variety of civil and military applications such as medical imaging, surveillance, night vision and astronomy applications. In IR systems, readout electronic is a key element between detector and signal processing units. System performance parameters of readout electronic can be enumerated as follows: signal-to-noise ratio (SNR), linearity, input referred noise level and dynamic range. In this thesis, design of a CMOS readout integrated circuit (ROIC) for an array of 6x7 as a part of 576x7 full ROIC system, p-on-n type mercury cadmium telluride (HgCdTe) long wave infrared (LWIR) detectors is presented. AMS 0.35 μ[micro]m, 4-metal 2-poly CMOS process is used in the design of ROIC. Preamplifier of ROIC is direct injection(DI) type due to noise performance. In order to increase SNR, time delay integration (TDI) on 7 detectors is applied with a supersampling rate of three. TDI stage implemented as current mode with current memories rather than capacitances to store integrated charges. This particular novel current mode TDI design in this thesis brings superior features over other topologies like high linearity, low area and very low power consumption in comparison with capacitor based topologies. 99.9% linearity is achieved with 2.5 times smaller area with very low power consumption (28 μ[micro]W per channel) compared to other topologies. ROIC has additional features of bidirectional TDI scanning, programmable five gain settings, and programmable integration time by serial/parallel interface. ROIC operated at 1 MHz with an output dynamic range of 3.75V and input referred noise of 1000 rms electrons

The Quanta Image Sensor: Every Photon Counts

The Quanta Image Sensor (QIS) was conceived when contemplating shrinking pixel sizes and storage capacities, and the steady increase in digital processing power. In the single-bit QIS, the output of each field is a binary bit plane, where each bit represents the presence or absence of at least one photoelectron in a photodetector. A series of bit planes is generated through high-speed readout, and a kernel or “cubicle” of bits (x, y, t) is used to create a single output image pixel. The size of the cubicle can be adjusted post-acquisition to optimize image quality. The specialized sub-diffraction-limit photodetectors in the QIS are referred to as “jots” and a QIS may have a gigajot or more, read out at 1000 fps, for a data rate exceeding 1 Tb/s. Basically, we are trying to count photons as they arrive at the sensor. This paper reviews the QIS concept and its imaging characteristics. Recent progress towards realizing the QIS for commercial and scientific purposes is discussed. This includes implementation of a pump-gate jot device in a 65 nm CIS BSI process yielding read noise as low as 0.22 e− r.m.s. and conversion gain as high as 420 µV/e−, power efficient readout electronics, currently as low as 0.4 pJ/b in the same process, creating high dynamic range images from jot data, and understanding the imaging characteristics of single-bit and multi-bit QIS devices. The QIS represents a possible major paradigm shift in image capture

Ultra-low noise, high-frame rate readout design for a 3D-stacked CMOS image sensor

Due to the switch from CCD to CMOS technology, CMOS based image sensors have become smaller, cheaper, faster, and have recently outclassed CCDs in terms of image quality. Apart from the extensive set of applications requiring image sensors, the next technological breakthrough in imaging would be to consolidate and completely shift the conventional CMOS image sensor technology to the 3D-stacked technology. Stacking is recent and an innovative technology in the imaging field, allowing multiple silicon tiers with different functions to be stacked on top of each other. The technology allows for an extreme parallelism of the pixel readout circuitry. Furthermore, the readout is placed underneath the pixel array on a 3D-stacked image sensor, and the parallelism of the readout can remain constant at any spatial resolution of the sensors, allowing extreme low noise and a high-frame rate (design) at virtually any sensor array resolution. The objective of this work is the design of ultra-low noise readout circuits meant for 3D-stacked image sensors, structured with parallel readout circuitries. The readout circuit’s key requirements are low noise, speed, low-area (for higher parallelism), and low power. A CMOS imaging review is presented through a short historical background, followed by the description of the motivation, the research goals, and the work contributions. The fundamentals of CMOS image sensors are addressed, as a part of highlighting the typical image sensor features, the essential building blocks, types of operation, as well as their physical characteristics and their evaluation metrics. Following up on this, the document pays attention to the readout circuit’s noise theory and the column converters theory, to identify possible pitfalls to obtain sub-electron noise imagers. Lastly, the fabricated test CIS device performances are reported along with conjectures and conclusions, ending this thesis with the 3D-stacked subject issues and the future work. A part of the developed research work is located in the Appendices.Devido à mudança da tecnologia CCD para CMOS, os sensores de imagem em CMOS tornam se mais pequenos, mais baratos, mais rápidos, e mais recentemente, ultrapassaram os sensores CCD no que respeita à qualidade de imagem. Para além do vasto conjunto de aplicações que requerem sensores de imagem, o próximo salto tecnológico no ramo dos sensores de imagem é o de mudar completamente da tecnologia de sensores de imagem CMOS convencional para a tecnologia “3D-stacked”. O empilhamento de chips é relativamente recente e é uma tecnologia inovadora no campo dos sensores de imagem, permitindo vários planos de silício com diferentes funções poderem ser empilhados uns sobre os outros. Esta tecnologia permite portanto, um paralelismo extremo na leitura dos sinais vindos da matriz de píxeis. Além disso, num sensor de imagem de planos de silício empilhados, os circuitos de leitura estão posicionados debaixo da matriz de píxeis, sendo que dessa forma, o paralelismo pode manter-se constante para qualquer resolução espacial, permitindo assim atingir um extremo baixo ruído e um alto debito de imagens, virtualmente para qualquer resolução desejada. O objetivo deste trabalho é o de desenhar circuitos de leitura de coluna de muito baixo ruído, planeados para serem empregues em sensores de imagem “3D-stacked” com estruturas altamente paralelizadas. Os requisitos chave para os circuitos de leitura são de baixo ruído, rapidez e pouca área utilizada, de forma a obter-se o melhor rácio. Uma breve revisão histórica dos sensores de imagem CMOS é apresentada, seguida da motivação, dos objetivos e das contribuições feitas. Os fundamentos dos sensores de imagem CMOS são também abordados para expor as suas características, os blocos essenciais, os tipos de operação, assim como as suas características físicas e suas métricas de avaliação. No seguimento disto, especial atenção é dada à teoria subjacente ao ruído inerente dos circuitos de leitura e dos conversores de coluna, servindo para identificar os possíveis aspetos que dificultem atingir a tão desejada performance de muito baixo ruído. Por fim, os resultados experimentais do sensor desenvolvido são apresentados junto com possíveis conjeturas e respetivas conclusões, terminando o documento com o assunto de empilhamento vertical de camadas de silício, junto com o possível trabalho futuro

Radiation Damage in CMOS Image Sensors for Space Applications

The space radiation environment is damaging to silicon devices, such as Complementary Metal Oxide Semiconductor (CMOS) image sensors, affecting their performance over time or causing total failure. The first part of this work investigates a Charge Coupled Device (CCD) style CMOS image sensor designed for TDI (Time Delay and Integration) mode imaging, a mode commonly used for Earth observation. Damage from high energy protons in the space environment decreases the Charge Transfer Efficiency (CTE) and increases the dark current of such devices. Experimental work on proton damaged devices is presented, showing the effects on CTE and dark current. The results are compared to a standard CCD by a simulation to take into account the different dimensions and operating conditions of the two devices. The second part of this work describes an experimental campaign to determine the effects of process variations (namely the introduction of deep doping wells and the variation of epitaxial silicon thickness) on the rate of Single Event Latchup (SEL) in CMOS Active Pixel Sensor (APS) devices. SEL is a potentially destructive phenomenon which occurs in CMOS technology but not in CCDs. Test devices were subjected to heavy ion bombardement and SEL rates recorded for a range of heavy ions causing varying amounts of ionisation. A simulation using Technology Computer Aided Design (TCAD) was developed to predict the SEL rates due to heavy ions and to understand the characteristic shape of the SEL cross section vs. Linear Energy Transfer (LET) curves produced by SEL experiments. The simuation was carried out for structures representative of each of the design variants

Predictive multiple sampling algorithm with overlapping integration intervals for linear wide dynamic range integrating image sensors

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2004.Includes bibliographical references (p. 163-170).This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.Machine vision systems are used in a wide range of applications such as security, automated quality control and intelligent transportation systems. Several of these systems need to extract information from natural scenes in the section of the electromagnetic spectrum visible to humans. These scenes can easily have intra-frame illumination ratios in excess of 10⁶ : 1. Solid-state image sensors that can correctly process wide illumination dynamic range scenes are therefore required to ensure correct reliability and performance. This thesis describes a new algorithm to linearly increase the illumination dynamic range of integrating-type image sensors. A user-defined integration time is taken as a reference to create a potentially large set of integration intervals of different duration (the selected integration time being the longest) but with a common end. The light intensity received by each pixel in the sensing array is used to choose the optimal integration interval from the set, while a pixel saturation predictive decision is used to overlap the integration intervals within the given integration time such that only one frame using the optimal integration interval for each pixel is produced. The total integration time is never exceeded. Benefits from this approach are motion minimization, real-time operation, reduced memory requirements, programmable light intensity dynamic range increase and access to incremental light intensity information during the integration time.(cont.) The algorithm is fully described with special attention to the resulting sensor transfer function, the signal-to-noise ratio, characterization of types and effects of errors in the predictive decision, calculation of the optimal integration intervals set given a certain set size, calculation of the optimal number of integration intervals, and impact of the new algorithm to image data compression. An efficient mapping of this algorithm to a CMOS process was done by designing a proof-of-concept integrated circuit in a 0.18[mu]m 1.8V 5-metal layer process. The major components of the chip are a 1/3" VGA (640 x 480) pixel array, a 4bit per pixel memory array, an integration controller array and an analog-to-digital converter/correlated double sampled (ADC/CDS) array. Supporting components include pixel and memory row decoders, memory and converter output digital multiplexers, pixel-to-ADC/CDS analog multiplexer and test structures. The pixels have a fill factor of nearly 50%, as most of the needed system additions and complexity were taken off-pixel. The prototype is fully functional and linearly expands the dynamic range by more than 60dB.by Pablo M. Acosta-Serafini.Ph.D

Analysis and design of a wide dynamic range pulse-frequency modulation CMOS image sensor

Complementary Metal-Oxide Semiconductor (CMOS) image sensor is the dominant electronic imaging device in many application fields, including the mobile or portable devices, teleconference cameras, surveillance and medical imaging sensors. Wide dynamic range (WDR) imaging is of interest particular, demonstrating a large-contrast imaging range of the sensor. As of today, different approaches have been presented to provide solutions for this purpose, but there exists various trade-offs among these designs, which limit the number of applications. A pulse-frequency modulation (PFM) pixel offers the possibility to outperform existing designs in WDR imaging applications, however issues such as uniformity and cost have to be carefully handled to make it practical for different purposes. In addition, a complete evaluation of the sensor performance has to be executed prior to fabrication in silicon technology. A thorough investigation of WDR image sensor based on the PFM pixel is performed in this thesis. Starting with the analysis, modeling, and measurements of a PFM pixel, the details of every particular circuit operation are presented. The causes of dynamic range (DR) limitations and signal nonlinearity are identified, and noise measurement is also performed, to guide future design strategies. We present the design of an innovative double-delta compensating (DDC) technique which increases the sensor uniformity as well as DR. This technique achieves performance optimization of the PFM pixel with a minimal cost an improved linearity, and is carefully simulated to demonstrate its feasibility. A quad-sampling technique is also presented with the cooperation of pixel and column circuits to generate a WDR image sensor with a reduced cost for the pixel. This method, which is verified through the field-programmable gate array (FPGA) implementation, saves considerable area in the pixel and employs the maximal DR that a PFM pixel provides. A complete WDR image sensor structure is proposed to evaluate the performance and feasibility of fabrication in silicon technology. The plans of future work and possible improvements are also presented

DESIGN OF A BURST MODE ULTRA HIGH-SPEED LOW-NOISE CMOS IMAGE SENSOR

Ultra-high-speed (UHS) image sensors are of interest for studying fast scientific phenomena and may also be useful in medicine. Several published studies have recently achieved frame rates of up to millions of frames per second (Mfps) using advanced processes and/or customized processes. This thesis presents a burst-mode (108 frames) UHS low-noise CMOS image sensor (CIS) based on charge-sweep transfer gates in an unmodified, standard 180 nm front-side-illuminated CIS process. By optimizing the photodiode geometry, the 52.8 μm pitch pixels with 20x20 μm^2 of active area, achieve a charge-transfer time of less than 10 ns. A proof-of-concept CIS was designed and fabricated. Through characterization, it is shown that the designed CIS has the potential to achieve 20 Mfps with an input-referred noise of 5.1 e− rms

Microfluidics for Biosensing and Diagnostics

Efforts to miniaturize sensing and diagnostic devices and to integrate multiple functions into one device have caused massive growth in the field of microfluidics and this integration is now recognized as an important feature of most new diagnostic approaches. These approaches have and continue to change the field of biosensing and diagnostics. In this Special Issue, we present a small collection of works describing microfluidics with applications in biosensing and diagnostics