Layout level design for testability strategy applied to a CMOS cell library

The layout level design for testability (LLDFT) rules used here allow to avoid some hard to detect faults or even undetectable faults on a cell library by modifying the cell layout without changing their behavior and achieving a good level of reliability. These rules avoid some open faults or reduce their appearance probability. The main purpose has been to apply that set of LLDFT rules on the cells of the library designed at the Centre Nacional de Microelectronica (CNM) in order to obtain a highly testable cell library. The authors summarize the main results (area overhead and performance degradation) of the application of the LLDFT rules on the cell

Testability enhancement of a basic set of CMOS cells

Testing should be evaluated as the ability of the test patterns to cover realistic faults, and high quality IC products demand high quality testing. We use a test strategy based on physical design for testability (to discover both open and short faults, which are difficult or even impossible to detect). Consequentially, layout level design for testability (LLDFT) rules have been developed, which prevent the faults, or at least reduce the chance of their appearing. The main purpose of this work is to apply a practical set of LLDFT rules to the library cells designed by the Centre Nacional de Microelectrònica (CNM) and obtain a highly testable cell library. The main results of the application of the LLDFT rules (area overheads and performance degradation) are summarized and the results are significant since IC design is highly repetitive; a small effort to improve cell layout can bring about great improvement in design

Developing VLSI Curricula in Electrical and Computer Engineering Department

© ASEE 2010VLSI (Very Large Scale Integrated Circuits) technology has enabled the information technology revolution which greatly changed the life style of human society. Computers, internet, cellphones, digital cameras/camcorders and many other consumer electronic products are powered by VLSI technology. In the past decades, the VLSI industry was constantly driven by the miniaturization of transistors. As governed by Moore’s law, the number of transistors in the same chip area has been doubled every 12 to 18 months. Nowadays, a typical VLSI CPU chip can contain millions to billions of transistors. As a result, the design of VLSI system is becoming more and more complex. Various EDA tools must be used to help the design of modern VLSI chips. The semiconductor and VLSI industry remain strong needs for VLSI engineers each year. In this paper, efforts in developing systematic VLSI curricula in Electrical and Computer Engineering department have been proposed. The goal of the curricula is to prepare students to satisfy the growing demands of VLSI industry as well as the higher education/research institutions. Modern VLSI design needs a thorough understanding about VLSI in device, gate, module and system levels. We developed CPEG/EE 448D: Introduction to VLSI to give students a comprehensive introduction about digital VLSI design and analysis. In this course, various EDA tools (such as Mentor Graphics tools, Cadence PSPICE, Synopsys) are used in the course projects to help students practice the VLSI design. In addition, analog and mixed signal circuit design are becoming more and more important as MEMS (Microelectromechanical Systems) and Nano devices are integrated with VLSI into Systemon-Chip (SoC) design. We developed CPEG/EE 458: Analog VLSI to introduce the analog and mixed signal VLSI design. As portable electronics (e.g. laptops, cellphones, PDAs, digital cameras) becoming more and more popular, low power VLSI circuit design is becoming a hot field. We developed CPEG/EE 548: Low Power VLSI Circuit Design to introduce various low power techniques to reduce the power consumption of VLSI circuits. Nowadays the VLSI circuits can contain billions of transistors, the testing of such complex system becoming more and more challenging. We developed CPEG/EE 549: VLSI Testing to introduce various VLSI testing strategies for modern VLSI design. In addition to the design and testing, we also developed EE 448: Microelectronic Fabrication to introduce the fabrication processes of modern VLSI circuits. With such a series of VLSI related curricula, students have an opportunity to learn comprehensive knowledge and hands-on experience about VLSI circuit design, testing, fabrication and EDA tools. Students demonstrate tremendous interests in the VLSI field, and all the VLSI courses are generally oversubscripted by students in the early stage of enrollment. Many students are also doing the VLSI graduate research and published various papers/posters in the VLSI related journals/conferences

Custom Integrated Circuits

Contains reports on nine research projects.Analog Devices, Inc.International Business Machines CorporationJoint Services Electronics Program Contract DAAL03-89-C-0001U.S. Air Force - Office of Scientific Research Contract AFOSR 86-0164BDuPont CorporationNational Science Foundation Grant MIP 88-14612U.S. Navy - Office of Naval Research Contract N00014-87-K-0825American Telephone and TelegraphDigital Equipment CorporationNational Science Foundation Grant MIP 88-5876

A design for testability study on a high performance automatic gain control circuit.

A comprehensive testability study on a commercial automatic gain control circuit is presented which aims to identify design for testability (DfT) modifications to both reduce production test cost and improve test quality. A fault simulation strategy based on layout extracted faults has been used to support the study. The paper proposes a number of DfT modifications at the layout, schematic and system levels together with testability. Guidelines that may well have generic applicability. Proposals for using the modifications to achieve partial self test are made and estimates of achieved fault coverage and quality levels presente

Custom Integrated Circuits

Contains reports on ten research projects.Analog Devices, Inc.IBM CorporationNational Science Foundation/Defense Advanced Research Projects Agency Grant MIP 88-14612Analog Devices Career Development Assistant ProfessorshipU.S. Navy - Office of Naval Research Contract N0014-87-K-0825AT&TDigital Equipment CorporationNational Science Foundation Grant MIP 88-5876

Testing a CMOS operational amplifier circuit using a combination of oscillation and IDDQ test methods

This work presents a case study, which attempts to improve the fault diagnosis and testability of the oscillation testing methodology applied to a typical two-stage CMOS operational amplifier. The proposed test method takes the advantage of good fault coverage through the use of a simple oscillation based test technique, which needs no test signal generation and combines it with quiescent supply current (IDDQ) testing to provide a fault confirmation. A built in current sensor (BICS), which introduces insignificant performance degradation of the circuit-under-test (CUT), has been utilized to monitor the power supply quiescent current changes in the CUT. The testability has also been enhanced in the testing procedure using a simple fault-injection technique. The approach is attractive for its simplicity, robustness and capability of built-in-self test (BIST) implementation. It can also be generalized to the oscillation based test structures of other CMOS analog and mixed-signal integrated circuits. The practical results and simulations confirm the functionality of the proposed test method

Programmable CMOS Analog-to-Digital Converter Design and Testability

In this work, a programmable second order oversampling CMOS delta-sigma analog-to-digital converter (ADC) design in 0.5µm n-well CMOS processes is presented for integration in sensor nodes for wireless sensor networks. The digital cascaded integrator comb (CIC) decimation filter is designed to operate at three different oversampling ratios of 16, 32 and 64 to give three different resolutions of 9, 12 and 14 bits, respectively which impact the power consumption of the sensor nodes. Since the major part of power consumed in the CIC decimator is by the integrators, an alternate design is introduced by inserting coder circuits and reusing the same integrators for different resolutions and oversampling ratios to reduce power consumption. The measured peak signal-to-noise ratio (SNR) for the designed second order delta-sigma modulator is 75.6dB at an oversampling ratio of 64, 62.3dB at an oversampling ratio of 32 and 45.3dB at an oversampling ratio of 16. The implementation of a built-in current sensor (BICS) which takes into account the increased background current of defect-free circuits and the effects of process variation on ΔIDDQ testing of CMOS data converters is also presented. The BICS uses frequency as the output for fault detection in CUT. A fault is detected when the output frequency deviates more than ±10% from the reference frequency. The output frequencies of the BICS for various model parameters are simulated to check for the effect of process variation on the frequency deviation. A design for on-chip testability of CMOS ADC by linear ramp histogram technique using synchronous counter as register in code detection unit (CDU) is also presented. A brief overview of the histogram technique, the formulae used to calculate the ADC parameters, the design implemented in 0.5µm n-well CMOS process, the results and effectiveness of the design are described. Registers in this design are replaced by 6T-SRAM cells and a hardware optimized on-chip testability of CMOS ADC by linear ramp histogram technique using 6T-SRAM as register in CDU is presented. The on-chip linear ramp histogram technique can be seamlessly combined with ΔIDDQ technique for improved testability, increased fault coverage and reliable operation