BrainFrame: A node-level heterogeneous accelerator platform for neuron simulations

Objective: The advent of High-Performance Computing (HPC) in recent years has led to its increasing use in brain study through computational models. The scale and complexity of such models are constantly increasing, leading to challenging computational requirements. Even though modern HPC platforms can often deal with such challenges, the vast diversity of the modeling field does not permit for a single acceleration (or homogeneous) platform to effectively address the complete array of modeling requirements. Approach: In this paper we propose and build BrainFrame, a heterogeneous acceleration platform, incorporating three distinct acceleration technologies, a Dataflow Engine, a Xeon Phi and a GP-GPU. The PyNN framework is also integrated into the platform. As a challenging proof of concept, we analyze the performance of BrainFrame on different instances of a state-of-the-art neuron model, modeling the Inferior- Olivary Nucleus using a biophysically-meaningful, extended Hodgkin-Huxley representation. The model instances take into account not only the neuronal- network dimensions but also different network-connectivity circumstances that can drastically change application workload characteristics. Main results: The synthetic approach of three HPC technologies demonstrated that BrainFrame is better able to cope with the modeling diversity encountered. Our performance analysis shows clearly that the model directly affect performance and all three technologies are required to cope with all the model use cases.Comment: 16 pages, 18 figures, 5 table

System on chip design of the nerve centres of the human neuroregulatory system

Introducción: El sistema neurorregulador humano es un sistema nervioso complejo compuesto por un grupo heterogéneo de centros nerviosos distribuidos a lo largo de la médula espinal. Estos centros actúan de forma autónoma, se comunican mediante interconexiones nerviosas y gobiernan y regulan el comportamiento de órganos en los seres humanos. Por más de 20 años se viene estudiando el sistema neurorregulador del tracto urinario inferior, responsable de los órganos y sistemas que intervienen en el proceso de micción. El objetivo de la investigación ha sido comprender el papel individual de cada centro para crear un modelo general del sistema neurorregulador capaz de operar a nivel de centro nervioso. Métodos: El modelo creado se ha formalizado mediante la teoría de sistemas multiagente de forma que cada agente modele el comportamiento de un centro nervioso. Su granularidad ha abierto la posibilidad de actuar a nivel de centro, lo cual ha sido especialmente interesante en el tratamiento de disfunciones. Resultados y discusión: En este trabajo se enriqueció este modelo teórico con un modelo arquitectural que lo hiciera adecuado para su implementación en hardware. A partir del nuevo modelo, se propuso el diseño system on chip de un procesador específico capaz de desempeñar las funciones de un centro nervioso. En conclusión, la investigación supuso un enfoque original con el objetivo final de crear un chip parametrizable, capaz de desarrollar cualquier función neurorreguladora, que pudiera ser implantable en el cuerpo y con capacidad para trabajar de forma coordinada con el sistema neurorregulador biológico.Introduction: The human neuroregulatory system is a complex nervous system composed of a heterogeneous group of nerve centres distributed along the spinal cord. These centres act autonomously, communicate through neural interconnections, and govern and regulate the behavior of organs in humans. For more than twenty years, the neuroregulatory system of the lower urinary tract has been studied, which controls the organs and systems involved in the urination process. Based on the study of the behavior and composition of the lower urinary tract, we have succeeded in isolating the centres involved in its functioning. The goal has been to understand the individual role played by each centre to create a general model of the neuroregulatory system capable of operating at the level of the nerve centre. Methods: The model has been created and formalized based on Multi-Agent Systems theory: each agent thus models the behaviour of a nerve centre. Its granularity opens up the possibility of acting at the level of the centre, of particular interest to treat dysfunctions. Results and discussion: The present study enriches this theoretical model with an architectural model that makes it suitable to implement in hardware. Based on this new model, we propose a System on Chip (SoC) design of a specific processor capable of performing a nerve centre’s functions. Although this processor can be entirely configured and programmed to adjust to the functioning of the different centres, the present work aimed at facilitating the understanding and validation of the proposal. We thus focused on the cortical-diencephalic centre, responsible for voluntary micturition. As conclusions, the research adopted an original approach with the aim of creating a configurable chip, capable of developing any neuroregulatory function, implantable in the body and being able to function in a coordinated way with the biological neuroregulatory system

BrainFrame: A node-level heterogeneous accelerator platform for neuron simulations

Objective. The advent of high-performance computing (HPC) in recent years has led to its increasing use in brain studies through computational models. The scale and complexity of such models are constantly increasing, leading to challenging computational requirements. Even though modern HPC platforms can often deal with such challenges, the vast diversity of the modeling field does not permit for a homogeneous acceleration platform to effectively address the complete array of modeling requirements. Approach. In this paper we propose and build BrainFrame, a heterogeneous acceleration platform that incorporates three distinct acceleration technologies, an Intel Xeon-Phi CPU

Semiconductor Memory Devices for Hardware-Driven Neuromorphic Systems

This book aims to convey the most recent progress in hardware-driven neuromorphic systems based on semiconductor memory technologies. Machine learning systems and various types of artificial neural networks to realize the learning process have mainly focused on software technologies. Tremendous advances have been made, particularly in the area of data inference and recognition, in which humans have great superiority compared to conventional computers. In order to more effectively mimic our way of thinking in a further hardware sense, more synapse-like components in terms of integration density, completeness in realizing biological synaptic behaviors, and most importantly, energy-efficient operation capability, should be prepared. For higher resemblance with the biological nervous system, future developments ought to take power consumption into account and foster revolutions at the device level, which can be realized by memory technologies. This book consists of seven articles in which most recent research findings on neuromorphic systems are reported in the highlights of various memory devices and architectures. Synaptic devices and their behaviors, many-core neuromorphic platforms in close relation with memory, novel materials enabling the low-power synaptic operations based on memory devices are studied, along with evaluations and applications. Some of them can be practically realized due to high Si processing and structure compatibility with contemporary semiconductor memory technologies in production, which provides perspectives of neuromorphic chips for mass production

Heterogeneous computing system with field programmable gate array coprocessor for decision tree learning

U ovom radu prikazan je heterogeni računalni sustav i novi hibridni algoritam za učenje stabla odluke Dataflow decision tree construction – DF‑DTC. Algoritam DF‑DTC zasnovan je na algoritmu C4.5. Heterogeni sustav sadrži koprocesor izveden programirljivim poljem logičkih elemenata (FPGA, engl. field programmable gate array). Razrada arhitekture koprocesora i hibridnog algoritma DF‑DTC provedena je metodologijom programsko-sklopovskog suobliokovanja. U koprocesoru je izvedena obrada nominalnih atributa skupa za učenje, a u algoritam su uvedene prilagodbe podatkovnih struktura, te podrška za višedtretveno izvođenje. Vrednovanje performansi provedeno je mjerenjem ukupnog vremena izvršavanja rada programa, te mjerenjem vremena izvršavanja ključnih dijelova algoritma. Pri vrednovanju su korišteni sintetički skupovi za učenje, te skupovi za učenje javno dostupni na UCI repozitoriju. Performanse DF‑DTC-a uspoređene su s performansama postojeće programske implementacije algoritma EC4.5. Ubrzanje obrade nominalnih atributa na DF‑DTC-u iznosi u prosjeku 3, 00 puta u usporedbi s programskom implementacijom EC4.5. Za cjelokupno izvršavanje programa najbolje ubrzanje iznosi 1, 18 puta. Izvedba DF‑DTC-a za pokazala je potencijal FPGA-a kao platforme za ubrzanje učenja stabla odluke