A 2x2 Bit Multiplier Using Hybrid 13T Full Adder with Vedic Mathematics Method

Various arithmetic circuits such as multipliers require full adder (FA) as the main block for the circuit to operate. Speed and energy consumption become very vital in design consideration for a low power adder. In this paper, a 2x2 bit Vedic multiplier using hybrid full adder (HFA) with 13 transistors (13T) had been designed successfully. The design was simulated using Synopsys Custom Tools in General Purpose Design Kit (GPDK) 90 nm CMOS technology process. In this design, four AND gates and two hybrid FA (HFAs) are cascaded together and each HFA is constructed from three modules. The cascaded module is arranged in the Vedic mathematics algorithm. This algorithm satisfied the requirement of a fast multiplication operation because of the vertical and crosswise architecture from the Urdhva Triyakbyam Sutra which reduced the number of partial products compared to the conventional multiplication algorithm. With the combination of hybrid full adder and Vedic mathematics, a new combination of multiplier method with low power and low delay is produced. Performance parameters such as power consumption and delay were compared to some of the existing designs. With a 1V voltage supply, the average power consumption of the proposed multiplier was found to be 22.96 µW and a delay of 161 ps

A Novel Hybrid Full Adder using 13 Transistors

Full adder is a basic and vital building block for various arithmetic circuits such as multipliers. In this paper, a hybrid 1-bit full adder using complementary metal-oxide semiconductor (CMOS) logic style had been designed. This hybrid adder divided into three modules. Module I is a three transistors XOR gate. Module II is a novel sum circuit which successfully modified with the usage of lesser number of transistors used. Module III is a carry circuit which uses the carry output of module I and several other input to generate carry output. Performance parameters such as power and delay were compared to some of the existing designs. With a 1.8V voltage supply, the average power consumption of proposed hybrid adder was found extremely low which is 2.09 μW and a very low delay of 350 ps. Design in both speed and energy consumption becomes even more significant as the wordlength of the adder increases. The full adder design is simulated using Tanner EDA version 16 using General Process Design Kit (GPDK) 250nm technology CMOS processes

1-Bit Full Adder Circuit using XOR-XNOR Cells with Power and Area Optimization

This paper revel a realization of a superior circuit design of 1 bit full adder. The circuit is planned and implemented by using planar DG –MOSFETs at 45 nm technology. In CPU, arithmetic logic unit (ALU) is the core heart.   The adder cell is the important and necessary unit of an ALU. In the present paper, an improved 1-bit full adder circuit is proposed that consumes lower power and reduced number of transistors. The proposed adder circuit consists of 9 transistors and called as 9-T adder cell.  The planar DG-MOSFETs are new emerging transistors which can work n nanometer range and overcome the short channel effects. The simulation of proposed circuit is done in tanner tool version 13.0 using level 54 model files. The simulation is done to compare power, power delay product with supply voltage. The result is also checked at room temperature. This circuit performance of the proposed circuits compared with other reported circuits in literatures and it is seen approximately more than 99.9% reduction in power consumption. Keywords: Low power; Area Efficent; Full Adder; GDI; Multiplexer

Multiple bit error correcting architectures over finite fields

This thesis proposes techniques to mitigate multiple bit errors in GF arithmetic circuits. As GF arithmetic circuits such as multipliers constitute the complex and important functional unit of a crypto-processor, making them fault tolerant will improve the reliability of circuits that are employed in safety applications and the errors may cause catastrophe if not mitigated. Firstly, a thorough literature review has been carried out. The merits of efficient schemes are carefully analyzed to study the space for improvement in error correction, area and power consumption. Proposed error correction schemes include bit parallel ones using optimized BCH codes that are useful in applications where power and area are not prime concerns. The scheme is also extended to dynamically correcting scheme to reduce decoder delay. Other method that suits low power and area applications such as RFIDs and smart cards using cross parity codes is also proposed. The experimental evaluation shows that the proposed techniques can mitigate single and multiple bit errors with wider error coverage compared to existing methods with lesser area and power consumption. The proposed scheme is used to mask the errors appearing at the output of the circuit irrespective of their cause. This thesis also investigates the error mitigation schemes in emerging technologies (QCA, CNTFET) to compare area, power and delay with existing CMOS equivalent. Though the proposed novel multiple error correcting techniques can not ensure 100% error mitigation, inclusion of these techniques to actual design can improve the reliability of the circuits or increase the difficulty in hacking crypto-devices. Proposed schemes can also be extended to non GF digital circuits

Design Of High Speed ALU Using Vedic Mathematics For Floating And Fixed Point Integers

In this paper, we present a contrast and also study of numerous adders. Adder's circuit is important for making numerous electronic systems. The Intricacy in VLSI design boosts when the level of combination rises. In this paper, Adder is designed making use of a various method which is based upon MUX based adder; pass transistor, as well as reasoning 2-T logic. The efficiency of the system relies on the efficiency of interior components that are shown in the system. Here, the internal elements should be created in such manner in which, they must take in less power with minimal dead time. The recommended circuit is much better than the existing method concerning area and also hold-up. In several high-performance computing systems such as Digital Signal processors, FIR filters, Microprocessors, and also Microcontrollers, the Multipliers are the key parts where the adders are the standard foundation. The layout as well as the implementation of various 32-bit adders likes Ripple Carry Adder (RCA), Carry Increment adder (CINA) and Lug bypass adder (CBYA) for various full adder cells is done using the Verilog HDL. The outcomes are obtained by implementing Verilog code in Xilinx 14.5 ISE for the Spartan 3E household device with rate quality -5

Design and Implementation of Low Power Time-To-Digital Converter using MGDI Technique

This paper introduces a novel Time to Digital Converter (TDC) architecture based on the Modified Gate Diffusion Input (MGDI) technique, which is derived from the well-established GDI method. Through the utilization of MGDI-based logic gates and digital circuitry, this innovative approach leads to a substantial reduction in the number of transistors required for implementation. As a result, it offers significant advantages in terms of circuit area, power consumption, and propagation delay, while simultaneously simplifying the complexity of the overall logic design. The functional blocks within the TDC have been optimized to efficiently process an internal clock frequency of 5MHz. This achievement is realized using cutting-edge 90nm MGDI technology, operating at a supply voltage of 1V. Practical implementation of this design can be carried out seamlessly with Cadence Virtuoso tools in the 90nm technology node. In essence, this research effort represents a promising advancement in the realm of time-to-digital conversion. By harnessing the capabilities of MGDI and its transistor-saving attributes, the proposed TDC not only enhances performance but also addresses critical concerns such as power efficiency and chip area utilization. These advancements make it a compelling choice for applications requiring precise time measurements, while the compatibility with contemporary technology nodes ensures its relevance and applicability in modern integrated circuit design

Hardware Obfuscation for Finite Field Algorithms

With the rise of computing devices, the security robustness of the devices has become of utmost importance. Companies invest huge sums of money, time and effort in security analysis and vulnerability testing of their software products. Bug bounty programs are held which incentivize security researchers for finding security holes in software. Once holes are found, software firms release security patches for their products. The semiconductor industry has flourished with accelerated innovation. Fabless manufacturing has reduced the time-to-market and lowered the cost of production of devices. Fabless paradigm has introduced trust issues among the hardware designers and manufacturers. Increasing dependence on computing devices in personal applications as well as in critical infrastructure has given a rise to hardware attacks on the devices in the last decade. Reverse engineering and IP theft are major challenges that have emerged for the electronics industry. Integrated circuit design companies experience a loss of billions of dollars because of malicious acts by untrustworthy parties involved in the design and fabrication process, and because of attacks by adversaries on the electronic devices in which the chips are embedded. To counter these attacks, researchers have been working extensively towards finding strong countermeasures. Hardware obfuscation techniques make the reverse engineering of device design and functionality difficult for the adversary. The goal is to conceal or lock the underlying intellectual property of the integrated circuit. Obfuscation in hardware circuits can be implemented to hide the gate-level design, layout and the IP cores. Our work presents a novel hardware obfuscation design through reconfigurable finite field arithmetic units, which can be employed in various error correction and cryptographic algorithms. The effectiveness and efficiency of the proposed methods are verified by an obfuscated Reformulated Inversion-less Berlekamp-Massey (RiBM) architecture based Reed-Solomon decoder. Our experimental results show the hardware implementation of RiBM based Reed-Solomon decoder built using reconfigurable field multiplier designs. The proposed design provides only very low overhead with improved security by obfuscating the functionality and the outputs. The design proposed in our work can also be implemented in hardware designs of other algorithms that are based on finite field arithmetic. However, our main motivation was to target encryption and decryption circuits which store and process sensitive data and are used in critical applications

FIR Filter IC Design Using Redundant Binary Number Systems

Conventional number systems is the weighted fixed positive radix number systems, where signed number uses the sign as a symbol followed by the number part either in magnitude or r’s complement form. Addition of conventional number systems requires carry propagation (serial signal propagation) from LSD to MSD and the addition time depends on word-length, which is the main limitation of the VLSI performance.But Redundant number systems (RNS) is to allow addition of two numbers in which no serial signal propagation is required along the adder; that is, the time duration of the operation is independent of length of the operands and is the time required for the addition of two digits. This is the advantage of RNS over conventional number systems. Because of this advantage, in this thesis it proposed to design an FIR filter based on RNS. In order to implement FIR filter, it is necessary to design adder, multiplier and D-FF. For implementation, the structural blocks are to be designed such as PPM adder, MMP subtractor, D-FF, Digit-serial multiplier.In this thesis, a 368.18MHZ 3-tap FIR filter and 80MHZ Box-car FIR filter be designed based on bottom-up design flow using CADENCE 5.1.41, cadence IC design environment. The design was based on the CMOS 90nm technology process. Bottom level transistors are used from gpdk090 library. The advantages of full custom are maximum circuit performance, minimum design size, and minimum high-volume production cost

Cryptography for Ultra-Low Power Devices

Ubiquitous computing describes the notion that computing devices will be everywhere: clothing, walls and floors of buildings, cars, forests, deserts, etc. Ubiquitous computing is becoming a reality: RFIDs are currently being introduced into the supply chain. Wireless distributed sensor networks (WSN) are already being used to monitor wildlife and to track military targets. Many more applications are being envisioned. For most of these applications some level of security is of utmost importance. Common to WSN and RFIDs are their severely limited power resources, which classify them as ultra-low power devices. Early sensor nodes used simple 8-bit microprocessors to implement basic communication, sensing and computing services. Security was an afterthought. The main power consumer is the RF-transceiver, or radio for short. In the past years specialized hardware for low-data rate and low-power radios has been developed. The new bottleneck are security services which employ computationally intensive cryptographic operations. Customized hardware implementations hold the promise of enabling security for severely power constrained devices. Most research groups are concerned with developing secure wireless communication protocols, others with designing efficient software implementations of cryptographic algorithms. There has not been a comprehensive study on hardware implementations of cryptographic algorithms tailored for ultra-low power applications. The goal of this dissertation is to develop a suite of cryptographic functions for authentication, encryption and integrity that is specifically fashioned to the needs of ultra-low power devices. This dissertation gives an introduction to the specific problems that security engineers face when they try to solve the seemingly contradictory challenge of providing lightweight cryptographic services that can perform on ultra-low power devices and shows an overview of our current work and its future direction