Improving single slope ADC and an example implemented in FPGA with 16.7 GHz equivalent counter clock frequency

Single slope ADC is a common building block in many ASCI or FPGA based front-end systems due to its simplicity, small silicon footprint, low noise interference and low power consumption. In single slope ADC, using a Gray code counter is a popular scheme for time digitization, in which the comparator output drives the clock (CK) port of a register to latch the bits from the Gray code counter. Unfortunately, feeding the comparator output into the CK-port causes unnecessary complexities and artificial challenges. In this case, the propagation delays of all bits from the counter to the register inputs must be matched and the counter must be a Gray code one. A simple improvement on the circuit topology, i.e., feeding the comparator output into the D-port of a register, will avoid these unnecessary challenges, eliminating the requirement of the propagation delay match of the counter bits and allowing the use of regular binary counters. This scheme not only simplifies current designs for low speeds and resolutions, but also opens possibilities for applications requiring higher speeds and resolutions. A multi-channel single slope ADC based on a low-cost FPGA device has been implemented and tested. The timing measurement bin width in this work is 60 ps, which would need a 16.7 GHz counter clock had it implemented with the conventional Gray code counter scheme. A 12-bit performance is achieved using a fully differential circuit making comparison between the input and the ramping reference, both in differential format

Gray-code TDC with improved linearity and scalability for LiDAR applications

This paper presents a TDC architecture based on a gray code oscillator with improved linearity, for FPGA implementations. The proposed architecture introduces manual routing as a method to improve the TDC linearity and precision, by controlling the gray code oscillator Datapath, which also reduces the need for calibration mechanisms. Furthermore, the proposed manual routing procedure improves the performance homogeneity across multiple TDC channels, enabling the use of the same calibration module across multiple channels, if further improved precision is required. The proposed TDC channel uses only 16 FPGA logic resources (considering the Xilinx 7 series platform), making it suitable for applications where a large number of measurement channels are required. To validate the proposed architecture and routing procedure, two channels were integrated with a coarse counter, a FIFO memory and an AXI interface, to assemble the pulse measurement unit. A comparison between the default routing implementation and the proposed manual routing has been performed, shown an improvement of 27% on the overall TDC single-shot precision. The implemented TDC achieved a 380 ps RMS resolution, a maximum DNL of 0.38 LSB and a peak-to-peak INL of 0.69 LSB, corresponding to a 21.7% and 70.4% improvement, respectively, when compared to the default design approach.FCT - Fundação para a Ciência e a Tecnologia(037902

Frequency band characteristics of tree-structured filter banks

A sub-band decomposition filter bank can be recursively used in a tree structure to divide the frequency domain into various subfrequency bands. The frequency bands of the sub-band signals have a counter intuitive order in such a decomposition. The authors show that the relationship between the frequency content and the index of a sub-band signal can be expressed by an extension of the Gray code

A Digital-to-Analog Converter Architecture for Multi-Channel Applications

Systems-on-chip with the capability of driving multiple analog voltages are useful for a variety of applications, including multiple actuator control for robotics applications, automated test equipment systems, industrial automation, programmable logic controllers, and satellite ywheel motor control. Such applications require a DAC for each analog output. A multi-channel architecture that saves power and area by sharing hardware is needed. This work introduces a new single-ramp multi-channel 12-bit DAC architecture. The architecture includes a low power Gray code counter, ramp generator, digital comparator, analog memory units, and control logic. The new multi-channel DAC architecture allows hardware sharing between multiple channels, and enables Systems-on-Chip to have multiple analog outputs for stimulating transducers or motors. The DAC architecture is to be used in a variety of space and defense applications as part of the BAE Systems RAD6000 microcontroller project

Digital plus analog output encoder

The disclosed encoder is adapted to produce both digital and analog output signals corresponding to the angular position of a rotary shaft, or the position of any other movable member. The digital signals comprise a series of binary signals constituting a multidigit code word which defines the angular position of the shaft with a degree of resolution which depends upon the number of digits in the code word. The basic binary signals are produced by photocells actuated by a series of binary tracks on a code disc or member. The analog signals are in the form of a series of ramp signals which are related in length to the least significant bit of the digital code word. The analog signals are derived from sine and cosine tracks on the code disc

Three-Dimensional Magnetohydrodynamics Simulations Of Counter-Helicity Spheromak Merging In The Swarthmore Spheromak Experiment

Recent counter-helicity spheromak merging experiments in the Swarthmore Spheromak Experiment (SSX) have produced a novel compact torus (CT) with unusual features. These include a persistent antisymmetric toroidal magnetic field profile and a slow, nonlinear emergence of the n = 1 tilt mode. Experimental measurements are inconclusive as to whether this unique CT is a fully merged field-reversed configuration (FRC) with strong toroidal field or a partially merged doublet CT configuration with both spheromak- and FRC-like characteristics. In this paper, the SSX merging process is studied in detail using three-dimensional resistive MHD simulations from the Hybrid Magnetohydrodynamics (HYM) code. These simulations show that merging plasmas in the SSX parameter regime only partially reconnect, leaving behind a doublet CT rather than an FRC. Through direct comparisons, we show that the magnetic structure in the simulations is highly consistent with the SSX experimental observations. We also find that the n = 1 tilt mode begins as a fast growing linear mode that evolves into a slower-growing nonlinear mode before being detected experimentally. A simulation parameter scan over resistivity, viscosity, and line-tying shows that these parameters can strongly affect the behavior of both the merging process and the tilt mode. In fact, merging in certain parameter regimes is found to produce a toroidal-field-free FRC rather than a doublet CT. (C) 2011 American Institute of Physics. [doi:10.1063/1.3660533

VIPER : a 25-MHz, 100-MIPS peak VLIW micro-processor

This paper describes the design and implementation of a very long instruction word (VLIW) microprocessor. The VIPER (VLIW integer processor) contains four pipelined functional units, and can achieve 100 MIPS peak performance at 25 MHz. The procesor is capable of performing multiway branch operations, two load/store operations and up to four ALU operations in each clock cycle, with full register file access to each functional unit. VIPER is the first VLIW microprocessor known that can achieve this level of performance. Designed in twelve months, the processor is integrated with an instruction cache controller and a data cache, requiring 450,000 transistors and a die size of 12.9 by 9.1 mm in a 1.2 µm technology

A linear lower bound for incrementing a space-optimal integer representation in the bit-probe model

We present the first linear lower bound for the number of bits required to be accessed in the worst case to increment an integer in an arbitrary space- optimal binary representation. The best previously known lower bound was logarithmic. It is known that a logarithmic number of read bits in the worst case is enough to increment some of the integer representations that use one bit of redundancy, therefore we show an exponential gap between space-optimal and redundant counters. Our proof is based on considering the increment procedure for a space optimal counter as a permutation and calculating its parity. For every space optimal counter, the permutation must be odd, and implementing an odd permutation requires reading at least half the bits in the worst case. The combination of these two observations explains why the worst-case space-optimal problem is substantially different from both average-case approach with constant expected number of reads and almost space optimal representations with logarithmic number of reads in the worst case.Comment: 12 pages, 4 figure