Continuous-time cascaded ΣΔ modulators for VDSL: A comparative study

This paper describes new cascaded continuous-time ΣΔ modulators intended to cope with very high-rate digital subscriber line specifications, i.e 12-bit resolution within a 20-MHz signal bandwidth. These modulators have been synthesized using a new methodology that is based on the direct synthesis of the whole cascaded architecture in the continuous-time domain instead of using a discrete-to-continuous time transformation as has been done in previous approaches. This method allows to place the zeroes/poles of the loop-filter transfer function in an optimal way and to reduce the number of analog components, namely, transconductors and/or amplifiers, resistors, capacitors and digital-to-analog converters. This leads to more efficient topologies in terms of circuitry complexity, power consumption and robustness with respect to circuit non-idealities. A comparison study of the synthesized architectures is done considering their sensitivity to most critical circuit error mechanisms. Time-domain behavioral simulations are shown to validate the presented approach.Ministerio de Educación y Ciencia TEC2004-01752/MI

Design of a 125 mhz tunable continuous-time bandpass modulator for wireless IF applications

Bandpass sigma-delta modulators combine oversampling and noise shaping to get very high resolution in a limited bandwidth. They are widely used in applications that require narrowband high-resolution conversion at high frequencies. In recent years interests have been seen in wireless system and software radio using sigma-delta modulators to digitize signals near the front end of radio receivers. Such applications necessitate clocking the modulators at a high frequency (MHz or above). Therefore a loop filter is required in continuous-time circuits (e.g., using transconductors and integrators) rather than discretetime circuits (e.g., using switched capacitors) where the maximum clocking rate is limited by the bandwidth of Opamp, switchÂs speed and settling-time of the circuitry. In this work, the design of a CMOS fourth-order bandpass sigma-delta modulator clocking at 500 MHz for direct conversion of narrowband signals at 125 MHz is presented. A new calibration scheme is proposed for the best signal-to-noise-distortion-ratio (SNDR) of the modulator. The continuous-time loop filter is based on Gm-C resonators. A novel transconductance amplifier has been developed with high linearity at high frequency. Qfactor of filter is enhanced by tunable negative impedance which cancels the finite output impendence of OTA. The fourth-order modulator is implemented using 0.35 mm triplemetal standard analog CMOS technology. Postlayout simulation in CADENCE demonstrates that the modulator achieves a SNDR of 50 dB (~8 bit) performance over a 1 MHz bandwidth. The modulatorÂs power consumption is 302 mW from supply power of ± 1.65V

Wide-bandwidth, high-resolution delta-sigma analog-to-digital converters

There is a significant need in recent mobile communication and wireless broadband systems for high-performance analog-to-digital converters (ADCs) that have wide bandwidth (BW>5-MHz) and high data rate (>100-Mbps). A delta-sigma ADC is recognized as a power-efficient ADC architecture when high resolution (>12-b) is required. This is due to several advantages of the delta-sigma ADC including relaxed anti-aliasing filter requirements, high signal-to-noise and distortion ratio (SNDR) and most importantly, reduced sensitivity to analog imperfections. In this thesis, several structures and design techniques are developed for the implementation of continuoustime (CT) and discrete-time (DT) delta-sigma ADCs. These techniques save the total power consumption, reduce the design complexity, and decrease the chip die area of delta-sigma modulators. First a 4th-order single stage CT delta-sigma ADC with a novel single-amplifier-biquad (SAB) based loop filter is presented. By utilizing the SAB networks in the loop filter of an Nth-order CT delta-sigma modulator, it requires only half the number of active amplifiers and feed-forward branches used in the conventional modulator architecture, thus decreasing the power consumption and area by reducing the number of amplifiers. The proposed scheme also enables the modulator to use a switch-capacitor (SC) adder due to the reduced number of feedforward branches to its summing block. As a sequence, it consumes less power compared to a conventional CT adder. With a 130-nm CMOS technology, the fabricated prototype IC achieves a dynamic range of 80 dB with 10 MHz signal bandwidth and analog power dissipation lower than 12 mW. Presented as the second scheme to save power consumption and chip die area in ΔΣ modulators is a new stage-sharing technique in a discrete-time 2-2 MASH ΔΣ ADC. The proposed technique shares all the active blocks of the modulator second stage with its first stage during the two non-overlapping clock phases. Measurement results show that the modulator designed in a 0.13-um CMOS technology achieves 76 dB SNDR over a 10 MHz conversion bandwidth dissipating less than 9 mW analog power

High-level synthesis of switched-capacitor, switched-current and continuous-time ΣΔ modulators using SIMULINK-based time-domain behavioral models

This paper presents a high-level synthesis tool for ΣΔ Modulators (ΣΔMs) that combines an accurate SIMULINK-based time-domain behavioral simulator with a statistical optimization core. Three different circuit techniques for the modulator implementation are considered: switched-capacitor, switched-current and continuous-time. The behavioral models of these circuits, that take into account the most critical limiting factors, have been incorporated into the SIMULINK environment by using S-function blocks, which drastically increase the computational efficiency. The precision of these models has been validated by electrical simulations using HSPICE and experimental measurements from several silicon prototypes. The combination of high accuracy, short CPU time and interoperability of different circuit models together with the efficiency of the optimization engine makes the proposed tool an advantageous alternative for ΣΔM synthesis. The implementation on the well-known MATLAB/SIMULINK platform brings numerous advantages in terms of data manipulation, processing capabilities, flexibility and simulation with other electronic subsystems. Moreover, this is the first tool dealing with the synthesis of ΣΔMs using both discrete-time and continuous-time circuit techniques.This work was supported by the EU IST Project 2001-34283/TAMES-2 and by the Spanish Ministry of Science and Education (with support from the European Regional Development Fund) under Contract TIC2001-0929 ADAVERE and TEC2004-01752/MIC.Peer reviewe

Design techniques for sigma-delta modulators in communications applications

Specialised design techniques for sigma-delta modulators are described in this thesis with all of the examples coming from modern communications systems. The noise shaping and the signal transfer functions can be optimised using a weighted least squares approach. Numerical problems arising in the optimisation as a result of high oversampling rates are overcome through the use a simple transformation. The application to digitising audio is discussed, with the conclusion that Butterworth response noise shaping is preferable to inverse Chebyshev noise shaping for audio applications. An example of optimising the signal transfer function to provide immunity to instability brought about by large out-of-band signals is also presented. The use of redundant arithmetic in the implementation of very high speed sigma-delta modulators is introduced, together with a DAC / filter combination suitable for reconstructing an analogue signal from the redundant arithmetic SDM. An improved topology for a speech compander is described which offers a number of significant advantages over existing published methods. This uses no external components for ac coupling or setting the response time-constant, yet is robust and insensitive to parasitic components and process variations. This has been integrated on a CMOS IC process and the results are compared with the high level simulations. A simulation method which allows the verification of switched-capacitor schematics with several orders of magnitude speed improvements over commercially available simulation tools is discussed. The method assumes ideal components, with internally controllable switches and reduces the schematic netlist to the few key equations that an experienced designer would derive manually. This process is fully automated and consequently is useful for providing confidence in implementations of complex SC systems

A survey on continuous-time modulators : theory, designs and implementations

Recently, delta-sigma modulation has become a widely applied technique for high-performance analog-to-digital conversion of narrow-band signals. Most of the early designs used discrete-time structure for good accuracy and good linearity. The transfer functions are independent of the clock frequency. However, high unity-gain bandwidths of the opamps are required to satisfy the settling accuracy required in the discrete-time designs. Continuous-time structure can potentially achieve higher clock frequency with less power consumption. the anti-aliasing filter can also be eliminated due to the anti-aliasing property of CT modulators. On the other hand, CT ADC have their own problems, such as jitter sensitivity and excess loop delay. In this thesis, the state-of-the-art of CT modulator is reviewed. The problems in the design of CT ADCs are analyzed and solutions to them are described. The theory, design and implementations of CT modulator will also be reviewed.Keywords: Continuous-Time, Delta-Sigm

A closed-loop digitally controlled MEMS gyroscope with unconstrained Sigma-Delta force-feedback

In this paper, we describe the system architecture and prototype measurements of a MEMS gyroscope system with a resolution of 0.025 degrees/s/root Hz. The architecture makes extensive use of control loops, which are mostly in the digital domain. For the primary mode both the amplitude and the resonance frequency are tracked and controlled. The secondary mode readout is based on unconstrained Sigma Delta force-feedback, which does not require a compensation filter in the loop and thus allows more beneficial quantization noise shaping than prior designs of the same order. Due to the force-feedback, the gyroscope has ample dynamic range to correct the quadrature error in the digital domain. The largely digital setup also gives a lot of flexibility in characterization and testing, where system identification techniques have been used to characterize the sensors. This way, a parasitic direct electrical coupling between actuation and readout of the mass-spring systems was estimated and corrected in the digital domain. Special care is also given to the capacitive readout circuit, which operates in continuous time

Novel structures for high-speed delta-sigma data converters

As CMOS processes keep scaling down devices, the maximum operating frequencies of CMOS devices increase, and hence circuits can process very wide band signals. Moreover, the small physical dimensions of transistors allow the placing of many more blocks into a single chip, including highly accurate analog blocks and complicated digital blocks, which can process audio to communication data. Nowadays, wideband and low-power data converter is mandatory for mobile applications which need a bridge between analog and digital blocks. In this dissertation, low-power and wideband techniques are proposed. An embedded-adder quantizer with dynamic preamplifier is proposed to achieve power-efficient operation. Various double-sampling schemes are studied, and novel schemes are presented to achieve wideband operation without noise folding effect. To reduce timing delay and idle tones, a high speed DEM which alternates two sets of comparator references is proposed. Multi-cell architecture is studied to insure higher performance when the number of modulators increases. 0.18 um double-poly/4-metal CMOS process was used to implement a prototype IC. 20 MHz signal bandwidth was achieved with a 320 MHz sampling clock. The peak SNDR was 63 dB. The figure-of-merit FoM = P/(2*BW*2[superscript ENOB]) was 0.35 pJ/conversion, with a 16 mW power consumption. Measurement results show that the proposed design ideas are useful for low-power and wideband delta-sigma modulators which have low OSR. A second-order noise-coupled modulator with an embedded-zero optimization was proposed to reduce power consumption by eliminating some of the integrators. This architecture makes easier the implementation of the small feedback capacitors for high OSR modulators

The design of a 250MHz CMOS bandpass sigma-delta A/D modulator with continuous-time circuitry

Master'sMASTER OF ENGINEERIN