4,191 research outputs found
Developing a framework of non-fatal occupational injury surveillance for risk control in palm oil mills
Non-fatal occupational injury (NFOI) and its risk factors have become a current global
concern. The need of research towards the relationship between occupational injury
and its risk factor is essential, to fulfil the purpose and setting the priority of
implementing safety preventive approaches at workplace. This research intended to
develop a framework of NFOI surveillance by using epidemiological data, noise
exposure data and NFOI data among palm oil mills’ workers. A total of 420
respondents who assigned in operation and processing areas (OP) (n=333) and general
or office workers (n=87) had voluntary participated in this research. A questionnaire
session with respondents was held to obtain epidemiological data and NFOI
information via validated questionnaire. Noise hazard monitoring was executed by
using Sound Level Meter (SLM) for environmental noise monitoring and Personal
Sound Dosimeter for personal noise monitoring. Gathered data were analysed in
quantitative method by using statistical software IBM SPSS Statistic version 21 and a
risk matrix table for injury risk rating evaluation. It was discovered that high noise
exposure level (≥ 85 dB[A]) was significantly associated with non-fatal occupational
injury among OP workers (φ=0.123, p<0.05) with OR=1.87 (95% CI, 1.080-3.235,
p<0.05). Risk rating for reported NFOI was at moderate level, with minor cuts and
scratches were the dominant type of injury (42.6%). Analysis of logistic regression
indicated that working in shift, not wearing protective gloves, health problems such as
shortness of breath and ringing in ears, and excessive noise level (≥ 85 dB[A]) were
the risk factors of NFOI in palm oil mills among OP workers. A framework of nonfatal
injury surveillance in palm oil mills was developed based on the findings with
integration of risk management process and injury prevention principles. This
framework is anticipated to help the management in decision making for preventive
actions and early detection of occupational health effects among workers
Fast synchronization 3R burst-mode receivers for passive optical networks
This paper gives a tutorial overview on high speed burst-mode receiver (BM-RX) requirements, specific for time division multiplexing passive optical networks, and design issues of such BM-RXs as well as their advanced design techniques. It focuses on how to design BM-RXs with short burst overhead for fast synchronization. We present design principles and circuit architectures of various types of burst-mode transimpedance amplifiers, burst-mode limiting amplifiers and burst-mode clock and data recovery circuits. The recent development of 10 Gb/s BM-RXs is highlighted also including dual-rate operation for coexistence with deployed PONs and on-chip auto reset generation to eliminate external timing-critical control signals provided by a PON medium access control. Finally sub-system integration and state-of-the-art system performance for 10 Gb/s PONs are reviewed
Design of Inverter Based CMOS Amplifiers in Deep Nanoscale Technologies
In this work, it is proposed a fully differential ring amplifier topology with a deadzone
voltage created by a CMOS resistor with a biasing circuit to increase the robustness over PVT
variations.
The study focuses on analyzing the performance of the ring amplifier over process,
temperature, and supply voltage variations, in order to guarantee a viable industrial employment
in a 7 nm FinFET CMOS technology node for being used as residue amplifier in ADCs.
A ring amplifier is a small modular amplifier, derived from a ring oscillator. It is simple
enough that it can quickly be designed using only a few inverters, capacitors, and switches. It can
amplify with rail-to-rail output swing, competently charge large capacitive loads using slew-based
charging, and scale well in performance according to process trends.
In typical process corner, a gain of 72 dB is achieved with a settling time of 150 ps.
Throughout the study, the proposed topology is compared with others presented in literature
showing better results over corners and presenting a faster response. The proposed topology isn’t
yet suitable for industry use, because it presents one corner significantly slower than the rest,
namely process corner FF 125 °C, and process corner FS -40 °C with a small oscillation
throughout the entire amplification period.
Nevertheless, it proved itself to be a promising technique, showing a high gain and a fast
settling without oscillation phase, with room for improvement.Neste trabalho, é proposta uma topologia de ring amplifier com a deadzone a ser criada
através de uma resistência CMOS com um circuito de polarização para aumentar a robustez para
as variações PVT.
O estudo foca-se em analisar a performance do ring amplifier nas variações de processo,
temperatura e tensão de alimentação, de forma a garantir um uso viável em indústria na tecnologia
de 7 nm FinFET CMOS, para ser usado como amplificador de resíduo em ADCs.
Um ring amplifier é um pequeno amplificador modular, derivado do ring oscillator. É
simples o suficiente para ser facilmente projetado usando apenas poucos inversores,
condensadores e interruptores. Consegue amplificar com rail-to-rail output swing, carregar
grandes cargas capacitivas com carregamento slew-based e escalar bem em termos de
performance de acordo com o processo.
No typical process corner, foi obtido um ganho de 72 dB com um tempo de estabilização
de 150 ps. Durante o estudo, a topologia proposta é comparada com outras presentes na literatura
mostrando melhores resultados over corners e apresentando uma resposta mais rápida. A
topologia proposta ainda não está preparada para uso industrial uma vez que apresenta um corner
significativamente mais lento que os restantes, nomeadamente, process corner FF 125 °C, e outro
process corner, FS -40 °C, com uma pequena oscilação durante todo o período de amplificação.
Todavia, provou ser uma técnica promissora, apresentando um ganho elevado e uma rápida
estabilização sem fase de oscilação, com espaço para melhoria
Strategies for enhancing DC gain and settling performance of amplifiers
The operational amplifier (op amp) is one of the most widely used and important building blocks in analog circuit design. High gain and high speed are two important properties of op amps because they determine the settling behavior of the op amps. As supply voltages decrease, the realization of high gain amplifiers with large Gain-Bandwidth-Products (GBW) has become challenging. The major focus in this dissertation is on the negative output impedance gain enhancement technique. The negative impedance gain enhancement technique offers potential for achieving very high gain and energy-efficient fast settling and is low-voltage compatible. Misconceptions that have limited the practical adoption of this gain enhancement technique are discussed. A new negative conductance gain enhancement technique was proposed. The proposed circuit generates a negative conductance with matching requirements for achieving very high DC gain that are less stringent than those for existing -g m gain enhancement schemes. The proposed circuit has potential for precise digital control of a very large DC gain. A prototype fully differential CMOS operational amplifier was designed and fabricated based on the proposed gain enhancement technique. Experimental results which showed a DC gain of 85dB and an output swing of 876mVp-p validated the fundamental performance characteristics of this technique. In a separate section, a new amplifier architecture with bandpass feedforward compensation is presented. It is shown that a bandpass feedforward path can be used to substantially extend the unity-gain-frequency of an operational amplifier. Simulation results predict significant improvements in rise time and settling performance and show that the bandpass compensation scheme is reasonably robust. In the final section, a new technique for asynchronous data recovery based upon using a delay line in the incoming data path is introduced. The proposed data recovery system is well suited for tight tolerance channels and coding systems supporting standards that limit the maximum number of consecutive 0\u27s and 1\u27s in a data stream. This system does not require clock recovery, suffers no loss of data during acquisition, has a reduced sensitivity to jitter in the incoming data and does not exhibit jitter enhancement associated with VCO tracking in a PLL
High-Gain Transimpedance Amplifier With DC Photodiode Current Rejection
This master\u27s thesis deals with the design of a differential high-gain transimpedance amplifier in TSMC\u27s 0.18 um mixed signal process that utilizes a DC photodiode current cancellation loop and a switching automatic gain control (AGC) with a bilinear gain curve. The amplifier is designed to satisfy the demands of Optical Coherence Tomography applications where the receiver is expected to measure the envelope power of an amplitude modulated sinusoidal optical signal that incorporates a large DC component. Methods of increasing dynamic range and gain linearity through the use of DC photodiode current cancellation and bilinear gain are explored. Effects of changing DC photodiode current on the overall system response is also demonstrated
- …