Design of a Low Power 70MHz-110MHz Harmonic Rejection Filter with Class-AB Output Stage

An FM transmitter becomes the new feature in recent portable electronic development. A low power, integrable FM transmitter filter IC is required to meet the demand of FM transmitting feature. A low pass filter using harmonic rejection technique along with a low power class-AB output buffer is designed to meet the current market requirements on the FM transmitter chip. A harmonic rejection filter is designed to filter FM square wave signal from 70MHz to 110MHz into FM sine wave signal. Based on Fourier series, the harmonic rejection technique adds the phase shifted square waves to achieve better THD and less high frequency harmonics. The phase shifting is realized through a frequency divider, and the summation is implemented through a current summation circuit. A RC low pass filter with automatic tuning is designed to further attenuate unwanted harmonics. In this work, the filter's post layout simulation shows -53dB THD and harmonics above 800MHz attenuation of -99dB. The power consumption of the filter is less than 0.7mW. Output buffer stage is implemented through a resistor degenerated transconductor and a class-AB amplifier. Feedforward frequency compensation is applied to compensate the output class-AB stage, which extends the amplifier's operating bandwidth. A fully balanced class-AB driver is proposed to unleash the driving capability of common source output transistors. The output buffer reaches -43dB THD at 110MHz with 0.63Vpp output swing and drives 1mW into 50 load. The power consumption of the output buffer is 7.25mW. By using harmonic rejection technique, this work realizes the 70MHz-110MHz FM carrier filtering using TSMC 0.18um nominal process. Above 800MHz harmonics are attenuated to below -95dB. With 1.2V supply, the total power consumption including output buffer is 7.95mW. The total die area is 0.946mm2

Mixed-signal integrated circuits design and validation for automotive electronics applications

Automotive electronics is a fast growing market. In a field primarily dominated by mechanical or hydraulic systems, over the past few decades there has been exponential growth in the number of electronic components incorporated into automobiles. Partly thanks to the advance in high voltage smart power processes in nowadays cars is possible to integrate both power/high voltage electronics and analog/digital signal processing circuitry thus allowing to replace a lot of mechanical systems with electro-mechanical or fully electronic ones. High level modeling of complex electronic systems is gaining importance relatively to design space exploration, enabling shorter design and verification cycles, allowing reduced time-to-market. A high level model of a resistor string DAC to evaluate nonlinearities has been developed in MATLAB environment. As a test case for the model, a 10 bit resistive DAC in 0.18um is designed and the results were compared with the traditional transistor level approach. Then we face the analysis and design of a fundamental block: the bandgap voltage reference. Automotive requirements are tough, so the design of the voltage reference includes a pre-regulation part of the battery voltage that allows to enhance overall performances. Moreover an analog integrated driver for an automotive application whose architecture exploits today’s trends of analog-digital integration allowing a greater range of flexibility allowing high configurability and fast prototipization is presented. We covered also the mixed-signal verification approach. In fact, as complexity increases and mixed-signal systems become more and more pervasive, test and verification often tend to be the bottleneck in terms of time effort. A complete flow for mixed-signal verification using VHDL-AMS modeling and Python scripting is presented as an alternative to complex transistor level simulations. Finally conclusions are drawn

Plasmonic color filter array, high performance analog to digital converter architectures and novel circuit techniques

Part I: Plasmonic color filters can be manufactured at lower cost since they can be fabricated in single lithographic process step as compared to Fabry-Perot based filters. In addition, they have narrow passband making resolving sharp features in sample spectrum possible. Due to these benefits, in this thesis, Plasmonic color filters are investigated as alternative to conventional color filters and their feasibility for spectroscopy demonstrated through reconstruction of 6 sample spectra by using a set of 20 color filters. The error in reconstructed sample spectra is less than 0.137 root mean squared error across all samples. Part II: A novel 12-bit pipelined successive approximation analog to digital converter is investigated for high speed data conversion. The design was implemented in TSMC 65nm process to demonstrate the feasibility of the architecture. Furthermore, a high dynamic range audio delta sigma modulator using pseudo-pseudo differential topology was investigated and feasibility simulated using TSMC 65nm process. In addition, various novel systems and circuit techniques including efficient calibration of feedback digital to analog converters, new boosted switch and push-pull source follower circuits were investigated to improve upon existing circuit topologies

Intrinsic Hardware Evolution on the Transistor Level

This thesis presents a novel approach to the automated synthesis of analog circuits. Evolutionary algorithms are used in conjunction with a fitness evaluation on a dedicated ASIC that serves as the analog substrate for the newly bred candidate solutions. The advantage of evaluating the candidate circuits directly in hardware is twofold. First, it may speed up the evolutionary algorithms, because hardware tests can usually be performed faster than simulations. Second, the evolved circuits are guaranteed to work on a real piece of silicon. The proposed approach is realized as a hardware evolution system consisting of an IBM compatible general purpose computer that hosts the evolutionary algorithm, an FPGA-based mixed signal test board, and the analog substrate. The latter one is designed as a Field Programmable Transistor Array (FPTA) whose programmable transistor cells can be almost freely connected. The transistor cells can be configured to adopt one out of 75 different channel geometries. The chip was produced in a 0.6µm CMOS process and provides ample means for the input and output of analog signals. The configuration is stored in SRAM cells embedded in the programmable transistor cells. The hardware evolution system is used for numerous evolution experiments targeted at a wide variety of different circuit functionalities. These comprise logic gates, Gaussian function circuits, D/A converters, low- and highpass filters, tone discriminators, and comparators. The experimental results are thoroughly analyzed and discussed with respect to related work

A wideband low-power continuous-time delta-sigma modulator for next generation wireless applications

Delta-Sigma (ΔΣ) analog-to-digital converters (ADCs) are widely used in wireless transceivers. Recently, continuous-time (CT) ΔΣ ADCs gain growing interest in wireless applications for their lower power consumption and wider input bandwidth as compared with the discrete-time (DT) counterparts. In this thesis, a wideband low-power CT ΔΣ modulator for next generation wireless applications is proposed to achieve 10-bit dynamic range within a 25 MHz signal bandwidth. On the system level, a low-power, mainly feed-forward architecture is used to realize the loop filter. Feed-in branches are added and optimized to eliminate the out-of-band peaking in the signal transfer function. On the circuit level, two-stage operational amplifiers with class-AB output stages are used to implement low-power active RC integrators. Capacitor tuning is used to compensate the variation of RC time constants. In addition, a fast current adder, an 11-level internal flash ADC and three current feedback DACs are also integrated on the chip which was manufactured in TSMC 0.18 μm CMOS technology. The test results show that the modulator draws less than 10 mA from the 1.8 V supply voltage

Design of clock and data recovery circuits for energy-efficient short-reach optical transceivers

Nowadays, the increasing demand for cloud based computing and social media services mandates higher throughput (at least 56 Gb/s per data lane with 400 Gb/s total capacity 1) for short reach optical links (with the reach typically less than 2 km) inside data centres. The immediate consequences are the huge and power hungry data centers. To address these issues the intra-data-center connectivity by means of optical links needs continuous upgrading. In recent years, the trend in the industry has shifted toward the use of more complex modulation formats like PAM4 due to its spectral efficiency over the traditional NRZ. Another advantage is the reduced number of channels count which is more cost-effective considering the required area and the I/O density. However employing PAM4 results in more complex transceivers circuitry due to the presence of multilevel transitions and reduced noise budget. In addition, providing higher speed while accommodating the stringent requirements of higher density and energy efficiency (< 5 pJ/bit), makes the design of the optical links more challenging and requires innovative design techniques both at the system and circuit level. This work presents the design of a Clock and Data Recovery Circuit (CDR) as one of the key building blocks for the transceiver modules used in such fibreoptic links. Capable of working with PAM4 signalling format, the new proposed CDR architecture targets data rates of 50−56 Gb/s while achieving the required energy efficiency (< 5 pJ/bit). At the system level, the design proposes a new PAM4 PD which provides a better trade-off in terms of bandwidth and systematic jitter generation in the CDR. By using a digital loop controller (DLC), the CDR gains considerable area reduction with flexibility to adjust the loop dynamics. At the circuit level it focuses on applying different circuit techniques to mitigate the circuit imperfections. It presents a wideband analog front end (AFE), suitable for a 56 Gb/s, 28-Gbaud PAM-4 signal, by using an 8x interleaved, master/ slave based sample and hold circuit. In addition, the AFE is equipped with a calibration scheme which corrects the errors associated with the sampling channels’ offset voltage and gain mismatches. The presented digital to phase converter (DPC) features a modified phase interpolator (PI), a new quadrature phase corrector (QPC) and multi-phase output with de-skewing capabilities.The DPC (as a standalone block) and the CDR (as the main focus of this work) were fabricated in 65-nm CMOS technology. Based on the measurements, the DPC achieves DNL/INL of 0.7/6 LSB respectively while consuming 40.5 mW power from 1.05 V supply. Although the CDR was not fully operational with the PAM4 input, the results from 25-Gbaud PAM2 (NRZ) test setup were used to estimate the performance. Under this scenario, the 1-UI JTOL bandwidth was measured to be 2 MHz with BER threshold of 10−4. The chip consumes 236 mW of power while operating on 1 − 1.2 V supply range achieving an energyefficiency of 4.27 pJ/bit

The 1991 3rd NASA Symposium on VLSI Design

Papers from the symposium are presented from the following sessions: (1) featured presentations 1; (2) very large scale integration (VLSI) circuit design; (3) VLSI architecture 1; (4) featured presentations 2; (5) neural networks; (6) VLSI architectures 2; (7) featured presentations 3; (8) verification 1; (9) analog design; (10) verification 2; (11) design innovations 1; (12) asynchronous design; and (13) design innovations 2