PixFEL: development of an X-ray diffraction imager for future FEL applications

A readout chip for diffraction imaging applications at new generation X-ray FELs (Free Electron Lasers) has been designed in a 65 nm CMOS technology. It consists of a 32 × 32 matrix, with square pixels and a pixel pitch of 110 µm. Each cell includes a low-noise charge sensitive amplifier (CSA) with dynamic signal compression, covering an input dynamic range from 1 to 104 photons and featuring single photon resolution at small signals at energies from 1 to 10 keV. The CSA output is processed by a time-variant shaper performing gated integration and correlated double sampling. Each pixel includes also a small area, low power 10-bit time-interleaved Successive Approximation Register (SAR) ADC for in-pixel digitization of the amplitude measurement. The channel can be operated at rates up to 4.5 MHz, to be compliant with the rates foreseen for future X-ray FEL machines. The ASIC has been designed in order to be bump bonded to a slim/active edge pixel sensor, in order to build the first demonstrator for the PixFEL (advanced X-ray PIXel cameras at FELs) imager

Time-to-digital converters and histogram builders in SPAD arrays for pulsed-LiDAR

Light Detection and Ranging (LiDAR) is a 3D imaging technique widely used in many applications such as augmented reality, automotive, machine vision, spacecraft navigation and landing. Pulsed-LiDAR is one of the most diffused LiDAR techniques which relies on the measurement of the round-trip travel time of an optical pulse back-scattered from a distant target. Besides the light source and the detector, Time-to-Digital Converters (TDCs) are fundamental components in pulsed-LiDAR systems, since they allow to measure the back-scattered photon arrival times and their performance directly impact on LiDAR system requirements (i.e., range, precision, and measurements rate). In this work, we present a review of recent TDC architectures suitable to be integrated in SPAD-based CMOS arrays and a review of data processing solutions to derive the TOF information. Furthermore, main TDC parameters and processing techniques are described and analyzed considering pulsed-LiDAR requirements

HCS12 based embedded PWM Controller for battery charger application

With present wireless communication revolution, possession of mobile phones, MP3 walkmans, Ipods, Ipadsthe convenience of quick and easy communication, information storage and search, the situation has also brought to concern certain issues regarding their operation. Every cell phone comes with a rechargeable battery and battery charger. The devices like PDA, MP3 Walkman, and digital cameras all require batteries to operate, adding to the importance of rechargeable batteries. The cellphone batteries get damaged due to overcharge and subsequent signal deterioration due to absence of charge. Overcharging the battery will lead to lessening the battery life. Li-ion and Ni-Cd batteries are well suited to portable devices like cell phones, walkmans, by virtue of their small size and weight. However, life cycles of the batteries are easily affected due to overcharging and undercharging.The reason being that overcharging damages the physical components of the battery. On the other hand undercharging reduces the energy capacity of a battery. Thus,arises the need for an intelligent voltage and current controlled PWM microcontroller based battery charger to prevent the overcharging. The battery charger application will include an electromagnetic interference filter,bridge rectifier,transformer,switching that operates with the help of a microcontroller unit of a PWM controller.A current detection block,voltage detection block and a temperature detection block are feedback through differential amplifiers into the Analog to Digital conversion unit of the microcontroller. Microcontroller facilitates advanced user interface. The application aims at efficient battery performance, safety and cost

Interval Bisection Quantization Circuit for an 8-Bit Analog to Digital Converter

A common type of analog to digital converter (ADC) is called the successive approximation ADC. It works by setting each bit in the digital output code individually and thus its conversion time is determined by the clock frequency and the resolution of the converter. A speed improvement may be made by using a quantization circuit that sets the entire output code at once. The goal of this project is to design such a quantization circuit based on the interval bisection algorithm. The circuit was designed using Cadence Schematic and Virtuoso and was simulated using spice. Spice simulations show that, on average, the circuit converts faster than the conventional successive approximation converter.Electrical and Computer Engineering, Department o

Design and Simulation of an 8-Bit Successive Approximation Register Charge-Redistribution Analog-To-Digital Converter

The thesis initially investigates the history of the monolithic ADCs. The next chapter explores the different types of ADCs available in the market today. Next, the operation of a 4-bit SAR ADC has been studied. Based on this analysis, an 8-bit charge-redistribution SAR ADC has been designed and simulated with Multisim (National Instruments, Austin, TX). The design is divided into different blocks which are individually implemented and tested. Level-1 SPICE MOSFET models representative of 5μm devices were used wherever individual MOSFETs were used in the design. Finally, the power dissipation during the conversion period was also estimated. The supply voltage for the ADC is 5V and the clock frequency is 500KHz

GSFC magnetic field experiment Explorer 43

The magnetic field experiment flown on Explorer 43 is described. The detecting instrument is a triaxial fluxgate magnetometer which is mounted on a boom with a flipping mechanism for reorienting the sensor in flight. An on-board data processor takes successive magnetometer samples and transmits differences to the telemetry system. By examining these differences in conjunction with an untruncated sample transmitted periodically, the original data may be uniquely reconstructed on the ground

Data logging multiple aviation sensors using a Motorala [sic] HC11 microcontroller

This project is part of the research and development of a microprocessor based integrated instrumentation system for light aircraft. It involves interfacing a Motorola HC 11 microcontroller with several sensor inputs. The project system is designed to data log battery voltage, cylinder head temperature, ambient temperature and engine RPM

MULTIPAC, a multiple pool processor and computer for a spacecraft central data system, phase 2 Final report

MULTIPAC, multiple pool processor and computer for deep space probe central data syste

Development of an image converter of radical design

A long term investigation of thin film sensors, monolithic photo-field effect transistors, and epitaxially diffused phototransistors and photodiodes to meet requirements to produce acceptable all solid state, electronically scanned imaging system, led to the production of an advanced engineering model camera which employs a 200,000 element phototransistor array (organized in a matrix of 400 rows by 500 columns) to secure resolution comparable to commercial television. The full investigation is described for the period July 1962 through July 1972, and covers the following broad topics in detail: (1) sensor monoliths; (2) fabrication technology; (3) functional theory; (4) system methodology; and (5) deployment profile. A summary of the work and conclusions are given, along with extensive schematic diagrams of the final solid state imaging system product

Computer recommendations for an automatic approach and landing system for V/STOL aircraft. Volume 1 - Computer recommendations

Evaluation of digital computer for V/STOL aircraft automatic approach and landing syste