A readout chip for diffraction imaging applications at new generation X-ray FELs (Free Electron

Lasers) has been designed in a 65 nm CMOS technology. It consists of a 32 × 32 matrix, with

square pixels and a pixel pitch of 110 µm. Each cell includes a low-noise charge sensitive amplifier

(CSA) with dynamic signal compression, covering an input dynamic range from 1 to 104 photons

and featuring single photon resolution at small signals at energies from 1 to 10 keV. The CSA

output is processed by a time-variant shaper performing gated integration and correlated double

sampling. Each pixel includes also a small area, low power 10-bit time-interleaved Successive

Approximation Register (SAR) ADC for in-pixel digitization of the amplitude measurement. The

channel can be operated at rates up to 4.5 MHz, to be compliant with the rates foreseen for future

X-ray FEL machines. The ASIC has been designed in order to be bump bonded to a slim/active

edge pixel sensor, in order to build the first demonstrator for the PixFEL (advanced X-ray PIXel

cameras at FELs) imager

Battignani, Giovanni

Benkechkache, Mohamed El Amine

Bettarini, Stefano

Casarosa, Giulia

Dalla Betta, Gian-Franco

Fabris, Lorenzo

Forti, Francesco

Giorgi, Marcello

Grassi, Marco

Lodola, Luca

Malcovati, Piero

Manghisoni, Massimo

Morsani, Fabio

Paladino, Antonio

Pancheri, Lucio

Paoloni, Eugenio

Ratti, Lodovico

Re, Valerio

Rizzo, Giuliana

Traversi, Gianluca

Vacchi, Carla

Verzellesi, G.

English

A readout chip for diffraction imaging applications at new generation X-ray FELs (Free Electron
Lasers) has been designed in a 65 nm CMOS technology. It consists of a 32 × 32 matrix, with
square pixels and a pixel pitch of 110 μm. Each cell includes a low-noise charge sensitive amplifier
(CSA) with dynamic signal compression, covering an input dynamic range from 1 to 104 photons
and featuring single photon resolution at small signals at energies from 1 to 10 keV. The CSA
output is processed by a time-variant shaper performing gated integration and correlated double
sampling. Each pixel includes also a small area, low power 10-bit time-interleaved Successive
Approximation Register (SAR) ADC for in-pixel digitization of the amplitude measurement. The
channel can be operated at rates up to 4.5 MHz, to be compliant with the rates foreseen for future
X-ray FEL machines. The ASIC has been designed in order to be bump bonded to a slim/active
edge pixel sensor, in order to build the first demonstrator for the PixFEL (advanced X-ray PIXel
cameras at FELs) imager

GRASSI, Marco

Archivio della ricerca- Università di Roma La Sapienza

PoS(Vertex 2016)065PixFEL: development of an X-ray diffraction imagerfor future FEL applicationsLuca Lodola∗,ab G. Batignani,e f M. A. Benkechkache,c S. Bettarini,e f G. Casarosa,e fG.-F. Dalla Betta,cd L. Fabris,i F. Forti,e f M. Giorgi,e f M. Grassi,ab P. Malcovati,abM. Manghisoni,bg F. Morsani, f A. Paladino,e f L. Pancheri,cd E. Paoloni,e f L. Ratti,abV. Re,bg G. Rizzo,e f G. Traversi,bg C. Vacchi,ab G. Verzellesidh and H. XucdaUniversità degli Studi di Paviavia Ferrata 1. 27100 Pavia, ItalybINFN Sezione di Paviavia Bassi 6, 27100 Pavia, ItalycUniversità di TrentoVia Sommarive 9, 38123 Povo (TN), ItalydTIFPAVia Sommarive 14, 38123 Povo (TN), ItalyeUniversità di PisaLargo Pontecorvo 3, 56127 Pisa, Italyf INFN Sezione di PisaLargo Pontecorvo 3, 56127 Pisa, ItalygUniversità di BergamoVia Marconi 5, 24044 Dalmine (BG), Italyh Università di Modena e ReggioVia Amendola 2, 42122, Modena, Italyi Oak Ridge National LaboratoryOak Ridge, TN, USAE-mail: luca.lodola01@universitadipavia.itA readout chip for diffraction imaging applications at new generation X-ray FELs (Free ElectronLasers) has been designed in a 65 nm CMOS technology. It consists of a 32× 32 matrix, withsquare pixels and a pixel pitch of 110 µm. Each cell includes a low-noise charge sensitive ampli-fier (CSA) with dynamic signal compression, covering an input dynamic range from 1 to 104 pho-tons and featuring single photon resolution at small signals at energies from 1 to 10 keV. The CSAoutput is processed by a time-variant shaper performing gated integration and correlated doublesampling. Each pixel includes also a small area, low power 10-bit time-interleaved SuccessiveApproximation Register (SAR) ADC for in-pixel digitization of the amplitude measurement. Thechannel can be operated at rates up to 4.5 MHz, to be compliant with the rates foreseen for futureX-ray FEL machines. The ASIC has been designed in order to be bump bonded to a slim/activeedge pixel sensor, in order to build the first demonstrator for the PixFEL (advanced X-ray PIXelcameras at FELs) imager.The 25th International workshop on vertex detectorsSeptember 26-30, 2016La Biodola, Isola d’Elba, ITALY∗Speaker.c© Copyright owned by the author(s) under the terms of the Creative CommonsAttribution-NonCommercial-NoDerivatives 4.0 International License (CC BY-NC-ND 4.0). http://pos.sissa.it/PoS(Vertex 2016)065PixFEL: development of an X-ray diffraction imager for future FEL application Luca Lodola1. IntroductionNew generation FEL facilities will be able to provide X-ray beams with unprecedented proper-ties in terms of peak brilliance, pulse duration and repetition rates, potentially revolutionizing manyresearch fields (e.g. structural biology and chemistry, material science and nuclear and molecularphysics) [1] [2] [3]. Specific X-ray imaging detectors need to be developed to fully exploit the po-tential of the new generation FEL and to match the challenging requirements in terms of space andamplitude resolution, input dynamic range, frame rate and frame storage capability. The PixFEL(advanced X-ray PIXel cameras at FELs) project, founded by INFN, in the long terms aims to de-velop a two-dimensional pixelated imaging camera for application at future FELs and to advancethe state-of-the-art of imaging instrumentation by exploring innovative solution and new technolo-gies. This will be achieved by bump bonding a large area focal plane detector to a dual layerfront-end chip. The latter will be the result of the vertical interconnection, with Through SiliconVia (TSV) techniques, between a first layer with analog front-end and ADC and second layer onlyreserved to memory and digital readout [4]. After the characterization of a first prototype front-end[5], a new chip has been designed and fabricated using a 65 nm CMOS technology. The chip con-sists of a 32× 32 square cells. This work will address the design of the 32× 32 readout chip, itsmain building blocks and their performance.2. PixFEL readout channelThe Chip layout consists of 32× 32 matrix. Each 110 µm× 110 µm pixel of the readoutchip includes a low noise charge sensitive amplifier with dynamic signal compression, a time-variant shaper with a trapezoidal weighting function, a small area, low power 10-bit SAR ADC andelementary digital blocks for channel control and data readout. The block diagram of the readoutchannel is shown in Fig. 1(a) and the layout in Fig. 1(b). In the following details of the blocks arediscussed.(a)CSASAR ADCDIGITALFILTER(b)Figure 1: Block diagram of the pixel readout channel (a) and its layout (b).1PoS(Vertex 2016)065PixFEL: development of an X-ray diffraction imager for future FEL application Luca Lodola2.1 Charge sensitive amplifierIn order to cover the wide input dynamic range (from 1 to 104 photons) as requested by FELapplications, while preserving at the same time a single photon resolution for small input signals(up to 20 photons), a nonlinear input-output characteristic is needed. The CSA has a nonlinearcharacteristic thanks to the dynamic change of its feedback capacitance with the voltage across it.Figure 2(a) shows that the feedback capacitor is a MOS varactor [6] and that it is split into fourdevices with the same channel length and different channel widths. By suitably controlling thethree switches through a two bit binary-to-thermometric decoder, the total area of the feedbackMOS capacitor is changed so as to make the amplifier capable of processing signals from photonsat 1, 2, 4, 10 keV, while preserving the input dynamic range of 1 to 104 photons in each photonenergy configuration. Figure 2(b) shows the simulation results of the input-output characteristic forall the four energy options. The expected non-linear transfer function can be noticed, with a highergain in the region where single photon resolution is required, shown in the inset of Fig. 2(b), and asmaller gain at large signal. The input signal interval of 1 to 104 fits into an output dynamic rangeof about 500 mV in all of the four possible sensitivity configurations.-LVT PMOS20 / 72 keVLVT PMOS20 / 74 keVLVT PMOS40 / 7LVT PMOS120 / 710 keVinQholesVoutSR(a)01002003004005000 2 103 4 103 6 103 8 103 1 1041 keV2 keV4 keV10 keVCSAOutputVoltage[mV]# of Photons05101520250 5 10 15 20 25(b)Figure 2: Schematic diagram of the charge sensitive amplifier (a) and its simulated input-output character-istic (b).2.2 Time variant filterHalf of the cell in the 32× 32 array incorporates the shaper already implemented and testedin the channel prototype, based on a transconductor and on the so called flip-capacitor filter (FCF)[7]. A design improvement of the time variant shaping stage has been included for comparisonin the other half of the array. A simplified schematic diagram of the new shaping stage, which isdesigned around the same forward gain block as the one used for the FCF (a two stage amplifierwith NMOS differential input [8]) is shown in Fig. 3(a). The new proposed architecture is basedon a Differential Gated Integrator (DGI), in which the input terminals are switched between the2PoS(Vertex 2016)065PixFEL: development of an X-ray diffraction imager for future FEL application Luca Lodolareference voltage (Vre f ) and the output of the CSA (VCSA) to obtain, by means of a correlateddouble sampling (CDS) technique, a trapezoidal weighting function. With reference to the timingdiagram of the switch control signals shown in Fig. 3(b), during the baseline integration interval,the non-inverting input of the DGI is connected to the output of the CSA, whereas the other terminalis shorted toVre f . In the signal settling interval, both the terminals are left floating while the charge+-S1aCS2bRCSAVSRCoVSRRrefVrefVS1bS2a(a) (b)Figure 3: Schematic diagram of the DGI (a) and time diagram for the DGI control signals (b).generated in the detector by the diffracted laser pulse from the FEL source induces a signal at theCSA input. A second integration is performed in the subsequent period, during which the invertinginput of the DGI is connected to the CSA output. At the end of this time interval, the amplitude ofthe output signal Vo is proportional to the difference between the CSA output level after the photonsignal arrival, V+CSA, and the baseline level, V−CSA,Vo(3τ) =Vre f +τRC(V+CSA−V−CSA), (2.1)where τ is the duration of each of the four time intervals in Fig. 3(b) and R and C are the resistanceand the capacitance in the scheme of Fig. 3(a). The shaper has also two selectable gains (i.e.two selectable feedback capacitances) in order to cover the full input dynamic range at rates of4.5 MHz (τ ≈ 55 ns) and 2.25 MHz (τ ≈ 110 ns). At the end of 3τ , Vo is sampled by the ADC andthe feedback capacitances of the charge sensitive amplifier and of the filter are reset.2.3 Time-interleaved 10-bit SAR ADCEach pixel includes a Successive Approximation Register (SAR) Analog-to-Digital Converter(ADC) for in pixel digitization of the amplitude signal at a sampling frequency in the megahertzrange, up to 5 MHz [9]. A 10-bit resolution has been chosen in order to guarantee a single pho-ton resolution at small signals and a quantization noise much lower than the limit imposed by thePoisson noise at large signals. The ADC is based on a charge redistribution architecture, imple-mented through a split capacitor DAC array in order to reduce the area and the input capacitance.Besides, a time-interleaved structure has been implemented to speed up the ADC operation andto relax the driving capability requested to the previous stage (the shaper). Each ADC has twocapacitive DACs. During each sampling period, the capacitors of one of the DACs are pre-charged3PoS(Vertex 2016)065PixFEL: development of an X-ray diffraction imager for future FEL application Luca LodolaC 2C 16C C 2C 16CVREFVinVREF1 VREF1C 2C 16C C 2C 16CDAC switch controlSAR logicb9 b8 b1 b0...VREF,COMPADC outputVDACCDAC1DAC2CclocktriggerVREF1 VREF1EoCCONV1,2(a)0 0 1 1 1 1 0 01 1 10 0 0 1 0 1 0 0 1Conversion on DAC1 Conversion on DAC2Time [ns](b)Figure 4: Simplified scheme of the time-interleaved SAR ADC (a) and simulated main signals during twoconsecutive conversions (b), the first giving as a result the digital word ’0011110101’ and the second giving’0100101001’.by the shaper output stage, while the sample stored in the capacitors of the other DAC during theprevious period is converted. Figure 4 shows a simplified scheme of the ADC architecture and themain ADC signals simulated during two consecutive conversions, also illustrating the interleavingoperation. The comparator has a pre-amplification stage introduced in order to minimize kickbacknoise effects [10], followed by a dynamic latched comparator. The input switches, through whichthe capacitive DACs are pre-charged to the shaper output voltage, have to cover a wide range [0.2;4PoS(Vertex 2016)065PixFEL: development of an X-ray diffraction imager for future FEL application Luca Lodola(a)0.20.30.40.50.60.70.80.9-100 0 100 200 300 400 500 600 700CSAOutput[V]Time [ns]104 ph @ 1 keVSignal injectionReset(b)Figure 5: Measured CSA input-output characteristic (a) and time response (b).1] V. In order to keep their on-conductance constant through the whole input range, a bootstrapswitch architecture has been used.3. Preliminary experimental resultsThe measurement campaign on the readout channel of the new 32×32 array chip is ongoing.Preliminary measurement results on single blocks are discussed in the following. These data arerepresentative of the behavior detected in a larger set of samples. The output of the CSA and ofthe shaper can be measured through four analog output pins. Figure 5(a) shows the measuredCSA input-output characteristic for photons at all the selectable energies (1, 2, 4, 10 keV). TheFigure 6: DGI time response to two input signals (10 and 100 photons), each obtained in the two availableintegration time configurations (50 ns and 100 ns).5PoS(Vertex 2016)065PixFEL: development of an X-ray diffraction imager for future FEL application Luca Lodolainput charge for this measurement is obtained by injecting at the preamplifier input a number ofelectrons from 0 to about 4×106, by means of an external voltage step with an amplitude from 0 Vto 1.2 V applied on an input capacitance (Cin j) included in each pixel and with a value selectablebetween 50 fF or 500 fF. This means that the whole input dynamic range of 104 photons can becovered only in the 1 keV gain configuration. As it can be noticed, the measured input-outputcharacteristic is in good agreement with the simulation results shown in Fig. 2(b), with a slightlyhigher gain for small signals in the 4 and 10 keV gain settings, probably due to poor modeling ofstray capacitances in the foundry design kit. Figure 5(b) shows the time response of the CSA at themaximum input signal of 104 photons: the response time and the reset time (from 10% to 90%) arerespectively about 41 ns and 55 ns, therefore complying with operation at rates up to 4.5 MHz.Fig. 6 shows the response of the shaper to two different input signals (10 and 100 photons). In thetwo cases, the response was taken both in the 50 ns and in the 100 ns integration time configuration.As it can be noticed, when operated at τ = 50 ns, the best operating point for the chip, the DGI cancomply with the target conversion rate of 4.5 MHz.4. ConclusionIn this paper, a 32×32 matrix readout chip for diffraction imaging applications at X-ray freeelectron lasers has been described. Each block of the readout channel has been presented. Thefirst circuit is a charge sensitive amplifier with dynamic signal compression, capable of fitting thewide input dynamic range from 1 to 104 into an output range of about 500 mV. Beside that, thepreamplifier charge sensitivity can be selected in order to adapt to four different photon energiesfrom 1 to 10 keV. Than an improved version of the time variant filter, based on a differential gatedarchitecture, was discussed. Eventually a 10-bit time interleaved SAR ADC for in-pixel digitizationwas presented. The chip was designed and fabricated in a 65 nm CMOS technology. Preliminaryresults of the chip characterization were shown. Some discrepancy between measurements andsimulation was found, but the collected data demonstrate the compatibility of the readout channelwith operation at the target rate of 4.5 MHz. The measurement campaign is still ongoing in orderto collect more statistics and to characterize the behavior of the full matrix.References[1] R. Xu, H. Jiang, C. Song, J.A. Rodriguez, Z. Huang, C.-C. Chen et al., "Single-shot three-dimensionalstructure determination of nanocrystals with femtosecond X-ray free-electron laser pulses", Nat.Commun., vol. 5, pp. 4061, 2014.[2] A. Barty, J. Küpper and H.N. Chapman, "Molecular Imaging Using X-Ray Free-Electron Lasers",Annual Review of Physical Chemistry, Vol. 64, pp. 415-435, 2013.[3] J. Feldhaus, M. Krikunova, M. Meyer, T. Möller, R. Moshammer, A. Rudenko et al., "AMO science atthe FLASH and European XFEL free-electron laser facilities", Journal of Physics B: Atomic,Molecular and Optical Physics, vol. 46, no. 16, pp. 164002, 2013.[4] L. Ratti, D. Comotti, L. Fabris, M. Grassi, L. Lodola, P. Malcovati et al., "PixFEL: developing a finepitch, fast 2D X-ray imager for the next generation X-FELs", Nucl. Instrum. Meth. A, vol. 796, pp.2-7, 2015.6PoS(Vertex 2016)065PixFEL: development of an X-ray diffraction imager for future FEL application Luca Lodola[5] L. Ratti, D. Comotti, L. Fabris, M. Grassi, L. Lodola, P. Malcovati et al., "A 2D imager for X-rayFELs with a 65 nm CMOS readout based on per-pixel signal compression and 10 bit A/Dconversion", Nucl. Instrum. Meth. A, vol. 831, pp. 301-308, 2016.[6] M. Manghisoni, D. Comotti, L. Gaioni, L. Ratti, V. Re, "Dynamic compression of the signal in acharge sensitive amplifier: from concept to design", IEEE Trans. Nucl. Sci., vol. 62, no. 5, pp.2318-2326, 2015.[7] L. Bombelli, C. Fiorini, S. Facchinetti, M. Porro, and G. De Vita, "A fast current readout strategy forthe XFEL DePFET detector", Nucl. Instrum. Meth. A, vol. 624, pp. 360-366, 2010.[8] F. Maloberti, "Analog design for CMOS VLSI sysitems", Kluwer Academic Publishers, 2003.[9] L. Lodola, "Interleaved SAR ADC for in-pixel conversion in future X-ray FEL application", 201511th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME), pp. 81- 84, 2015.[10] P. M. Figueiredo, J. C. Vital, "Kickback Noise Reduction Techniques for CMOS LatchedComparators", IEEE Transactions On Circuits And SystemsâA˘TˇII: express briefs, Vol. 53, No. 7, July20067

PixFEL: development of an X-ray diffraction imager for future FEL applications

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