Design And Simulation Of Cmos-Based Bandgap Reference Voltage With Compensation Circuit Using 0.18 Μm Process Technology

Voltage reference circuit is important in electronic world nowadays. A CMOS based bandgap reference (BGR) circuit is preferred due to its size is smaller and consume less power. However, the drawback is the reference voltage variation of CMOS based BGR circuit is big in wide range of temperature, thus the temperature coefficient of it is high. Hence, an improved version of piecewise curvature-corrected Bandgap voltage reference circuit which has low voltage variation in wide range of temperature is introduced in this project to overcome the problem mentioned above. The BGR circuit is designed using CMOS compatible process in 0.18μm CMOS process technology and simulated by using Cadence tool. The proposed piecewise curvature-corrected BGR operate properly with output voltage of 558.6 mV to 558.3 mV by varying the voltage supply 1.4 V to 3.3 V at 27°C and the line regulation is 0.016% . Besides that, the best temperature coefficient obtained is 9.2 ppm/°C in the temperature range of -25°C to 150°C at 1.8 V. The PSSR of the proposed circuit is -69.91 dB at frequency less 10 kHz. The layout design of the proposed circuit is done by using Silterra 0.18 μm standard CMOS process and total die area is 0.0175 mm2 and temperature coefficient obtained in post layout simulation is 11.66ppm/°C. In short, it is found that the proposed design of BGR circuit is able to achieve high temperature range and relatively low voltage variation

Low Power, High PSR CMOS Voltage References

With integration of various functional modules such as radio frequency (RF) circuits, power management, and high frequency digital and analog circuits into one system on chip (SoC) in recent applications, power supply noise can cause significant system performance deterioration. This makes supply noise rejection of the embedded voltage reference crucial in modern SoC applications. Also the use of resistors in bandgap voltage references makes them less suitable for modern low power and portable applications. This thesis introduces two resistorless sub-1 V, all MOSFET references. The goal is to achieve a high power supply rejection (PSR) over a wide bandwidth not achieved in previous works. This high PSR over wide bandwidth is achieved by using a combination of a feedback technique and an innovative compact MOSFET low pass filter. The two references were fabricated in a standard 0.18 µm CMOS process. The first reference uses a composite transistor in subthreshold to produce a proportional-to-absolute temperature (PTAT) voltage which is converted to a current used to thermally compensate the threshold voltage of a MOSFET in saturation. The second references uses dynamic-threshold voltage MOSFET (DTMOS) to produce a PTAT voltage which is converted to a current used to thermally compensate the threshold voltage of a MOSFET in saturation. The measurement shows that both references consumes a sub-1 µW power across their entire operating temperatures. The first reference achieves a PSR better than 50 dB for frequencies of up to 70 MHz and a 20 ppm/°C temperature coefficient (TC) for temperatures from -35 °C — 80 °C. It has a compact area of 0.0180 mm2 and operates on a supply of 1.2 V — 2.3 V. The second reference achieves a PSR better than 50 dB for frequencies of up to 60 MHz. This reference achieves a TC of 9.33 ppm/°C after trimming for temperatures from -30 °C — 110 °C and a line regulation of 0.076 %/V for a step from 0.8 V to 2 V supply voltage with 360 nW power consumption at room temperature. It has a compact area of 0.0143 mm^2

A low-power native NMOS-based bandgap reference operating from −55°C to 125°C with Li-Ion battery compatibility

Summary The paper describes the implementation of a bandgap reference based on native-MOSFET transistors for low-power sensor node applications. The circuit can operate from −55°C to 125°C and with a supply voltage ranging from 1.5 to 4.2 V. Therefore, it is compatible with the temperature range of automotive and military-aerospace applications, and for direct Li-Ion battery attach. Moreover, the circuit can operate without any dedicated start-up circuit, thanks to its inherent single operating point. A mathematical model of the reference circuit is presented, allowing simple portability across technology nodes, with current consumption and silicon area as design parameters. Implemented in a 55-nm CMOS technology, the voltage reference achieves a measured average (maximum) temperature coefficient of 28 ppm/°C (43 ppm/°C) and a measured sample-to-sample variation within 57 mV, with a current consumption of 420 nA at 27°C

A low noise, sub-1ppm/oC piecewise second-order curvature compensated bandgap reference for high resolution ADC

학위논문 (석사) -- 서울대학교 대학원 : 공과대학 전기·정보공학부, 2020. 8. 김수환.본 논문에서는 고해상도 analog to digital converter를 위한 저 잡음, 고 정밀 bandgap voltage reference를 제안한다. reference 회로의 성능 중 가장 중요한 것들은 바로 낮은 온도 계수(temperature coefficient)와 저주파 대역의 전기적 잡음이다. 제안된 Bandgap reference 회로는 위 두가지 요소를 개선 하였다. 먼저 낮은 온도 계수를 성취하기 위해서는 BJT Emitter-Base전압의 비선형적 온도의존성을 보상해주어야 하고, bandgap core을 이루는 Error amplifier의 DC offset을 제거해야 하며, 마지막으로 process variation에의한 추가적인 온도 의존성을 상쇄시켜야 한다. 제안된 bandgap reference는 여러가지 회로 기술들을 활용해 위 요소들을 보상하였다. BJT Emitter-Base전압의 비선형적 온도 의존성을 온도에 대해 2차 의존성을 갖는 compensation 전류를 생성하고 bandgap core에 흘려주어 제거하였다. Compensation 전류는 크게 current subtraction 동작과 current squaring 동작을 통해 생성되는데, 위 동작은 모두 process variation에 둔감하다. 두 번 째로 process variation에 의한 온도 특성의 변화를 보상해 주기 위해 trimming resistor를 사용하였다. 마지막으로 error amplifier에 chopping을 적용하여 Error amplifier DC offset을 약화시켰다. Bandgap reference의 저 주파수 전기적 잡음의 근원은 대부분 Error amplifier이므로 chopping 동작을 통해 저주파대역의 전기적 잡음 또한 제거된다. Chopping 동작을 통해 생겨난 리플 과, 고주파 대역으로 변조된 저주파 대역의 전기적 잡음은 RC filter를 통해 제거하였다. 제안된 bandgap reference는 스탠다드 0.13um CMOS 공정의 3.3V 전원 소자로 설계하였으며 레이아웃 사이즈는 0.0534mm2이다. Post layout simulation 결과 제안된 bandgap reference의 -40°C부터 125°C 사이의 온도 계수는 약 0.64ppm/°C이다. 0.1Hz부터 10Hz사이의 integrated noise는 약 2.7uVrms이다. 제안된 bandgap reference는 상온에서 약 44uA의 전류를 소모한다.In this thesis a low noise and high precision bandgap reference is presented. One of the most important characteristics of reference circuit for analog to digital converter with high resolution is low temperature drift and low noise. The proposed bandgap reference improves these two characteristics. To achieve low temperature coefficient(TC), non-linear temperature dependence of emitter-base voltage of bipolar transistor should be compensated. Also, degradation of TC due to dc offset of the error amplifier and process variation is another concern. The proposed bandgap reference compensates these factors by utilizing various circuit technique. Because non-linear temperature dependence of bipolar transistor has a concave shape with temperature, second order curvature compensation current is generated by using current subtraction circuit and current squaring circuit and injected into bandgap core. The current subtraction and squaring operation is tolerant to process variation. To achieve low temperature coefficient regardless of process variation, PTAT trimming is utilized to compensate added linear temperature dependence. At last, to remove dc offset of the error amplifier, chopping technique is applied to the error amplifier. Ripple and up-modulated low frequency caused by chopping operation is removed through RC-filter. The proposed bandgap reference is designed in 0.13um standard CMOS process. Layout size of the bandgap reference is 0.0534mm2. Post layout simulation shows that TC of the bandgap reference from -40°C to 125 °C is 0.64ppm/°C. In addition, integrated noise from 0.1Hz to 10Hz is about 2.7uVrms. The proposed bandgap reference consumes 44uA at room temperature제 1 장 서론 1 제 1 절 연구의 배경 1 제 2 절 기본적인 bandgap reference의 동작 원리. 4 1. bipolar 트랜지스터의 온도 특성 4 2. 기본적인 bandgap voltage reference의 동작 원리 7 3. 기본적인 bandgap current reference의 동작 원리 9 제 2 장 기본적인 bandgap reference의 성능적 한계 12 제 1 절 비선형적 온도 의존성 12 1. error amplifier dc offset 14 2. emitter-base 전압의 비선형적 온도 의존성 16 3. bipolar 트랜지스터 전류 이득에 의한 비선형적 온도 의존성 17 4. bipolar 트랜지스터의 베이스 저항에 의한 비선형적 온도 의존성 19 제 2 절 Bandgap reference의 전기적 잡음. 20 제 3 장 제안하는 저 잡음 고 정밀 bandgap voltage reference 22 제 1절 제안된 bandgap reference의 전체 구조 22 1. PTAT전류 생성 회로 23 2. reference 전류 생성 회로 24 3. bandgap core 25 제 2절 Curvature compensation technique 25 제 3절 Noise reduction technique 30 제 4절 Resistor trimming 32 제 5절 주요 성분 파라 미터 테이블 33 제 4 장 Layout 및 모의 실험 결과 34 제 1 절 Layout 34 제 2 절 모의 실험 결과 35 제 5 장 결론 40 제 6 장 부록 current squaring 회로의 동작 원리. 41 참고문헌 43 Abstract 43Maste

Ultra-low power mixed-signal frontend for wearable EEGs

Electronics circuits are ubiquitous in daily life, aided by advancements in the chip design industry, leading to miniaturised solutions for typical day to day problems. One of the critical healthcare areas helped by this advancement in technology is electroencephalography (EEG). EEG is a non-invasive method of tracking a person's brain waves, and a crucial tool in several healthcare contexts, including epilepsy and sleep disorders. Current ambulatory EEG systems still suffer from limitations that affect their usability. Furthermore, many patients admitted to emergency departments (ED) for a neurological disorder like altered mental status or seizures, would remain undiagnosed hours to days after admission, which leads to an elevated rate of death compared to other conditions. Conducting a thorough EEG monitoring in early-stage could prevent further damage to the brain and avoid high mortality. But lack of portability and ease of access results in a long wait time for the prescribed patients. All real signals are analogue in nature, including brainwaves sensed by EEG systems. For converting the EEG signal into digital for further processing, a truly wearable EEG has to have an analogue mixed-signal front-end (AFE). This research aims to define the specifications for building a custom AFE for the EEG recording and use that to review the suitability of the architectures available in the literature. Another critical task is to provide new architectures that can meet the developed specifications for EEG monitoring and can be used in epilepsy diagnosis, sleep monitoring, drowsiness detection and depression study. The thesis starts with a preview on EEG technology and available methods of brainwaves recording. It further expands to design requirements for the AFE, with a discussion about critical issues that need resolving. Three new continuous-time capacitive feedback chopped amplifier designs are proposed. A novel calibration loop for setting the accurate value for a pseudo-resistor, which is a crucial block in the proposed topology, is also discussed. This pseudoresistor calibration loop achieved the resistor variation of under 8.25%. The thesis also presents a new design of a curvature corrected bandgap, as well as a novel DDA based fourth-order Sallen-Key filter. A modified sensor frontend architecture is then proposed, along with a detailed analysis of its implementation. Measurement results of the AFE are finally presented. The AFE consumed a total power of 3.2A (including ADC, amplifier, filter, and current generation circuitry) with the overall integrated input-referred noise of 0.87V-rms in the frequency band of 0.5-50Hz. Measurement results confirmed that only the proposed AFE achieved all defined specifications for the wearable EEG system with the smallest power consumption than state-of-art architectures that meet few but not all specifications. The AFE also achieved a CMRR of 131.62dB, which is higher than any studied architectures.Open Acces

A Piecewise Linear Approximation D/A Converter for Small Format LCD Applications

Low power operation is a driving requirement for the advancement of portable consumer electronics. As products get smaller and have more functionality the device integration requirements get tighter. This is certainly true of small format LCD applications like PDAs and cell phones. Recent advances in LCD technology have allowed for advanced circuitry to be built on the glass. This allows for the unique opportunity to integrate the LCD column driver with other circuitry rather than the traditional flip chip mounting on the glass. The integration of these D/A converters with digital circuitry presents a new set of design considerations. These considerations allow for the exploration of non-traditional architectures and algorithms. This work will explore these design considerations in detail and present a novel algorithm for conversion as well as a system implementation of this algorithm. The system implementation is compared to a standard linear converter to weigh the relative advantages of each. A high performance dynamically biased amplifier is developed for use in the D/A converter. This amplifier has a high slew rate while consuming a small amount of quiescent power

Estudio del diseño de un circuito de voltaje de referencia para aplicaciones de bajo voltaje y bajo consumo de energía

Este trabajo de investigación describe el funcionamiento de los circuitos que permiten la generación de un voltaje de referencia estable ante variaciones en la temperatura y el voltaje de alimentación. Las topologías clásicas de circuitos de voltaje de referencia limitan el voltaje que entregan a valores cercanos a 1.2 V, impidiendo que aplicaciones de menor voltaje puedan hacer uso de dichos circuitos. El principal inconveniente yace en que las topologías clásicas de estos circuitos limitan el voltaje que entregan a valores cercanos a 1.2 V. Actualmente muchos circuitos integrados se diseñan para operar con voltajes menores a 1.2 V, de modo que es necesario plantear las consideraciones que permitan el diseño de un circuito de voltaje de referencia de bajo voltaje. El propósito de este trabajo de investigación es exponer los fundamentos para el diseño de un circuito de voltaje de referencia. Se desarrolla la teoría que permite la obtención de un voltaje independiente de la temperatura. Posteriormente se analizan dos topologías: una convencional y otra de bajo voltaje. Esta última sirve de referencia para el diseño de voltaje de referencia de bajo voltaje. En la parte final de esta investigación se enuncian conclusiones sobre el marco teórico revisado. También se mencionan recomendaciones para el diseño de un circuito de bajo voltaje.Trabajo de investigació

Integrated Circuits for Programming Flash Memories in Portable Applications

Smart devices such as smart grids, smart home devices, etc. are infrastructure systems that connect the world around us more than before. These devices can communicate with each other and help us manage our environment. This concept is called the Internet of Things (IoT). Not many smart nodes exist that are both low-power and programmable. Floating-gate (FG) transistors could be used to create adaptive sensor nodes by providing programmable bias currents. FG transistors are mostly used in digital applications like Flash memories. However, FG transistors can be used in analog applications, too. Unfortunately, due to the expensive infrastructure required for programming these transistors, they have not been economical to be used in portable applications. In this work, we present low-power approaches to programming FG transistors which make them a good candidate to be employed in future wireless sensor nodes and portable systems. First, we focus on the design of low-power circuits which can be used in programming the FG transistors such as high-voltage charge pumps, low-drop-out regulators, and voltage reference cells. Then, to achieve the goal of reducing the power consumption in programmable sensor nodes and reducing the programming infrastructure, we present a method to program FG transistors using negative voltages. We also present charge-pump structures to generate the necessary negative voltages for programming in this new configuration

An accurate, trimless, high PSRR, low-voltage, CMOS bandgap reference IC

Bandgap reference circuits are used in a host of analog, digital, and mixed-signal systems to establish an accurate voltage standard for the entire IC. The accuracy of the bandgap reference voltage under steady-state (dc) and transient (ac) conditions is critical to obtain high system performance. In this work, the impact of process, power-supply, load, and temperature variations and package stresses on the dc and ac accuracy of bandgap reference circuits has been analyzed. Based on this analysis, the a bandgap reference that 1. has high dc accuracy despite process and temperature variations and package stresses, without resorting to expensive trimming or noisy switching schemes, 2. has high dc and ac accuracy despite power-supply variations, without using large off-chip capacitors that increase bill-of-material costs, 3. has high dc and ac accuracy despite load variations, without resorting to error-inducing buffers, 4. is capable of producing a sub-bandgap reference voltage with a low power-supply, to enable it to operate in modern, battery-operated portable applications, 5. utilizes a standard CMOS process, to lower manufacturing costs, and 6. is integrated, to consume less board space has been proposed. The functionality of critical components of the system has been verified through prototypes after which the performance of the complete system has been evaluated by integrating all the individual components on an IC. The proposed CMOS bandgap reference can withstand 5mA of load variations while generating a reference voltage of 890mV that is accurate with respect to temperature to the first order. It exhibits a trimless, dc 3-sigma accuracy performance of 0.84% over a temperature range of -40°C to 125°C and has a worst case ac power-supply ripple rejection (PSRR) performance of 30dB up to 50MHz using 60pF of on-chip capacitance. All the proposed techniques lead to the development of a CMOS bandgap reference that meets the low-cost, high-accuracy demands of state-of-the-art System-on-Chip environments.Ph.D.Committee Chair: Rincon-Mora, Gabriel; Committee Member: Ayazi, Farrokh; Committee Member: Bhatti, Pamela; Committee Member: Leach, W. Marshall; Committee Member: Morley, Thoma