Implicit feed-forward compensated op-amp with split pairs

Disclosed are systems implementing an implicit Feed-Forward Compensated (FFC) op-amp, where the main FFC port is realized by the P-side of the CMOS input structure of the 2nd and 3rd stages of the op-amp, while the main signal path is through the N-side. According to some embodiments, to balance the relative strengths of the main path and feed-forward paths, the 2nd-stage NMOS input pair is split into two pairs, one is used to route the main path while the other is used for auxiliary FFC. The disclosed implicit FCC op-amp is unconditionally stable with adequate phase lead. According to some embodiments, the disclosed op-amp, which may be a wide-band op-amp, can be used in highly linear applications operative at intermediate frequency (IF), such as signal buffers for high-performance data converters or radio-frequency (RF) modulators and demodulators, continuous-time (CT) filters or sigma-delta data converters.Board of Regents, University of Texas Syste

Frequency compensation of CMOS operational amplifier.

Ho Kin-Pui.Thesis (M.Phil.)--Chinese University of Hong Kong, 2002.Includes bibliographical references (leaves 92-95).Abstracts in English and Chinese.Abstract --- p.2摘要 --- p.4Acknowledgements --- p.5Table of Contents --- p.6List of Figures --- p.10List of Tables --- p.14Chapter Chapter 1 --- Introduction --- p.15Overview --- p.15Objective --- p.17Thesis Organization --- p.17Chapter Chapter 2 --- Fundamentals of Operational Amplifier --- p.19Chapter 2.1 --- Definitions of Commonly Used Figures --- p.19Chapter 2.1.1 --- Input Differential Voltage Range --- p.19Chapter 2.1.2 --- Maximum Output Voltage Swing --- p.20Chapter 2.1.3 --- Input Common Mode Voltage Range --- p.20Chapter 2.1.4 --- Input Offset Voltage --- p.20Chapter 2.1.5 --- Gain Bandwidth Product --- p.21Chapter 2.1.6 --- Phase Margin --- p.22Chapter 2.1.7 --- Slew Rate --- p.22Chapter 2.1.8 --- Settling Time --- p.23Chapter 2.1.9 --- Common Mode Rejection Ratio --- p.23Chapter 2.2 --- Frequency Compensation of Operational Amplifier --- p.24Chapter 2.2.1 --- Overview --- p.24Chapter 2.2.2 --- Miller Compensation --- p.25Chapter Chapter 3 --- CMOS Current Feedback Operational Amplifier --- p.27Chapter 3.1 --- Introduction --- p.27Chapter 3.2 --- Current Feedback Operational Amplifier with Active Current Mode Compensation --- p.28Chapter 3.2.1 --- Circuit Description --- p.29Chapter 3.2.2 --- Small Signal analysis --- p.32Chapter 3.2.3 --- Simulation Results --- p.34Chapter Chapter 4 --- Reversed Nested Miller Compensation --- p.38Chapter 4.1 --- Introduction --- p.38Chapter 4.2 --- Frequency Response --- p.39Chapter 4.2.1 --- Gain-bandwidth product --- p.40Chapter 4.2.2 --- Right half complex plane zero --- p.40Chapter 4.2.3 --- The Pair of Complex Conjugate Poles --- p.42Chapter 4.3 --- Components Sizing --- p.47Chapter 4.4 --- Circuit Simulation --- p.48Chapter Chapter 5 --- Enhancement Technique for Reversed Nested Miller Compensation --- p.54Chapter 5.1 --- Introduction --- p.54Chapter 5.2 --- Working principle of the proposed circuit --- p.54Chapter 5.2.1 --- The introduction of nulling resistor --- p.55Chapter 5.2.2 --- The introduction of a voltage buffer --- p.55Chapter 5.2.3 --- Small Signal Analysis --- p.57Chapter 5.2.4 --- Sign Inversion of the RHP Zero with Nulling Resistor --- p.59Chapter 5.2.5 --- Frequency Multiplication of the Complex Conjugate Poles --- p.60Chapter 5.2.6 --- Stability Conditions --- p.63Chapter 5.3 --- Performance Comparison --- p.67Chapter 5.4 --- Conclusion: --- p.70Chapter 5.4.1 --- Circuit Modifications: --- p.70Chapter 5.4.2 --- Advantages: --- p.71Chapter Chapter 6 --- Physical Design of Operational Amplifier --- p.72Chapter 6.1 --- Introduction --- p.72Chapter 6.2 --- Transistor Layout Techniques --- p.72Chapter 6.2.1 --- Multi-finger Layout Technique --- p.72Chapter 6.2.2 --- Common-Centroid Structure --- p.73Chapter 6.3 --- Layout Techniques of Passive Components --- p.74Chapter 6.3.1 --- Capacitor Layout --- p.74Chapter 6.3.2 --- Resistor Layout --- p.75Chapter Chapter 7 --- Measurement Results --- p.77Chapter 7.1 --- Overview --- p.77Chapter 7.2 --- Measurement Results for the Current Feedback Operational Amplifier --- p.77Chapter 7.2.1 --- Frequency Response of the inverting amplifier --- p.77Chapter 7.3 --- Measurement Results for the Three-Stage Operational Amplifier --- p.80Chapter 7.3.1 --- Input Offset Voltage Measurement --- p.80Chapter 7.3.2 --- Input Common Mode Range Measurement --- p.80Chapter 7.3.3 --- Gain Band width Measurement --- p.81Chapter 7.3.4 --- DC Gain measurement --- p.85Chapter 7.3.5 --- Slew Rate Measurement --- p.87Chapter 7.3.6 --- Phase Margin --- p.88Chapter 7.3.7 --- Performance Summary --- p.89Chapter Chapter 8 --- Conclusions --- p.90Chapter Chapter 9 --- Appendix --- p.9

Developing a framework of non-fatal occupational injury surveillance for risk control in palm oil mills

Non-fatal occupational injury (NFOI) and its risk factors have become a current global concern. The need of research towards the relationship between occupational injury and its risk factor is essential, to fulfil the purpose and setting the priority of implementing safety preventive approaches at workplace. This research intended to develop a framework of NFOI surveillance by using epidemiological data, noise exposure data and NFOI data among palm oil mills’ workers. A total of 420 respondents who assigned in operation and processing areas (OP) (n=333) and general or office workers (n=87) had voluntary participated in this research. A questionnaire session with respondents was held to obtain epidemiological data and NFOI information via validated questionnaire. Noise hazard monitoring was executed by using Sound Level Meter (SLM) for environmental noise monitoring and Personal Sound Dosimeter for personal noise monitoring. Gathered data were analysed in quantitative method by using statistical software IBM SPSS Statistic version 21 and a risk matrix table for injury risk rating evaluation. It was discovered that high noise exposure level (≥ 85 dB[A]) was significantly associated with non-fatal occupational injury among OP workers (φ=0.123, p<0.05) with OR=1.87 (95% CI, 1.080-3.235, p<0.05). Risk rating for reported NFOI was at moderate level, with minor cuts and scratches were the dominant type of injury (42.6%). Analysis of logistic regression indicated that working in shift, not wearing protective gloves, health problems such as shortness of breath and ringing in ears, and excessive noise level (≥ 85 dB[A]) were the risk factors of NFOI in palm oil mills among OP workers. A framework of nonfatal injury surveillance in palm oil mills was developed based on the findings with integration of risk management process and injury prevention principles. This framework is anticipated to help the management in decision making for preventive actions and early detection of occupational health effects among workers

A 0.1–5.0 GHz flexible SDR receiver with digitally assisted calibration in 65 nm CMOS

© 2017 Elsevier Ltd. All rights reserved.A 0.1–5.0 GHz flexible software-defined radio (SDR) receiver with digitally assisted calibration is presented, employing a zero-IF/low-IF reconfigurable architecture for both wideband and narrowband applications. The receiver composes of a main-path based on a current-mode mixer for low noise, a high linearity sub-path based on a voltage-mode passive mixer for out-of-band rejection, and a harmonic rejection (HR) path with vector gain calibration. A dual feedback LNA with “8” shape nested inductor structure, a cascode inverter-based TCA with miller feedback compensation, and a class-AB full differential Op-Amp with Miller feed-forward compensation and QFG technique are proposed. Digitally assisted calibration methods for HR, IIP2 and image rejection (IR) are presented to maintain high performance over PVT variations. The presented receiver is implemented in 65 nm CMOS with 5.4 mm2 core area, consuming 9.6–47.4 mA current under 1.2 V supply. The receiver main path is measured with +5 dB m/+5dBm IB-IIP3/OB-IIP3 and +61dBm IIP2. The sub-path achieves +10 dB m/+18dBm IB-IIP3/OB-IIP3 and +62dBm IIP2, as well as 10 dB RF filtering rejection at 10 MHz offset. The HR-path reaches +13 dB m/+14dBm IB-IIP3/OB-IIP3 and 62/66 dB 3rd/5th-order harmonic rejection with 30–40 dB improvement by the calibration. The measured sensitivity satisfies the requirements of DVB-H, LTE, 802.11 g, and ZigBee.Peer reviewedFinal Accepted Versio

Design of a Torque Current Generator for Strapdown Gyroscopes

The design, analysis, and experimental evaluation of an optimum performance torque current generator for use with strapdown gyroscopes, is presented. Among the criteria used to evaluate the design were the following: (1) steady-state accuracy; (2) margins of stability against self-oscillation; (3) temperature variations; (4) aging; (5) static errors drift errors, and transient errors, (6) classical frequency and time domain characteristics; and (7) the equivalent noise at the input of the comparater operational amplifier. The DC feedback loop of the torque current generator was approximated as a second-order system. Stability calculations for gain margins are discussed. Circuit diagrams are shown and block diagrams showing the implementation of the torque current generator are discussed

High Gain Amplifier with Enhanced Cascoded Compensation

A two-stage CMOS operational amplifier with both, gain-boosting and indirect current feedback frequency compensation performed by means of regulated cascode amplifiers, is presented. By using quasi-floating-gate transistors (QFGT) the supply requirements, the number of capacitors and the size of the compensation capacitors respect to other Miller schemes are reduced. A prototype was fabricated using a 0.5 μm technology, resulting, for a load of 45 pF and supply voltage of 1.65 V, in open-loop-gain of 129 dB, 23 MHz of gain-bandwidth product, 60o phase margin, 675 μW power consumption and 1% settling time of 28 ns

CMOS design of chaotic oscillators using state variables: a monolithic Chua's circuit

This paper presents design considerations for monolithic implementation of piecewise-linear (PWL) dynamic systems in CMOS technology. Starting from a review of available CMOS circuit primitives and their respective merits and drawbacks, the paper proposes a synthesis approach for PWL dynamic systems, based on state-variable methods, and identifies the associated analog operators. The GmC approach, combining quasi-linear VCCS's, PWL VCCS's, and capacitors is then explored regarding the implementation of these operators. CMOS basic building blocks for the realization of the quasi-linear VCCS's and PWL VCCS's are presented and applied to design a Chua's circuit IC. The influence of GmC parasitics on the performance of dynamic PWL systems is illustrated through this example. Measured chaotic attractors from a Chua's circuit prototype are given. The prototype has been fabricated in a 2.4- mu m double-poly n-well CMOS technology, and occupies 0.35 mm/sup 2/, with a power consumption of 1.6 mW for a +or-2.5-V symmetric supply. Measurements show bifurcation toward a double-scroll Chua's attractor by changing a bias current

Novel active function blocks and their applications in frequency filters and quadrature oscillators

Kmitočtové filtry a sinusoidní oscilátory jsou lineární elektronické obvody, které jsou používány v široké oblasti elektroniky a jsou základními stavebními bloky v analogovém zpracování signálu. V poslední dekádě pro tento účel bylo prezentováno velké množství stavebních funkčních bloků. V letech 2000 a 2006 na Ústavu telekomunikací, VUT v Brně byly definovány univerzální proudový konvejor (UCC) a univerzální napět'ový konvejor (UVC) a vyrobeny ve spolupráci s firmou AMI Semiconductor Czech, Ltd. Ovšem, stále existuje požadavek na vývoj nových aktivních prvků, které nabízejí nové výhody. Hlavní přínos práce proto spočívá v definici dalších původních aktivních stavebních bloků jako jsou differential-input buffered and transconductance amplifier (DBTA), current follower transconductance amplifier (CFTA), z-copy current-controlled current inverting transconductance amplifier (ZC-CCCITA), generalized current follower differential input transconductance amplifier (GCFDITA), voltage gain-controlled modified current-feedback operational amplifier (VGC-MCFOA), a minus-type current-controlled third-generation voltage conveyor (CC-VCIII-). Pomocí navržených aktivních stavebních bloků byly prezentovány původní zapojení fázovacích článků prvního řádu, univerzální filtry druhého řádu, ekvivalenty obvodu typu KHN, inverzní filtry, aktivní simulátory uzemněného induktoru a kvadraturní sinusoidní oscilátory pracující v proudovém, napět'ovém a smíšeném módu. Chování navržených obvodů byla ověřena simulací v prostředí SPICE a ve vybraných případech experimentálním měřením.Frequency filters and sinusoidal oscillators are linear electric circuits that are used in wide area of electronics and also are the basic building blocks in analogue signal processing. In the last decade, huge number of active building blocks (ABBs) were presented for this purpose. In 2000 and 2006, the universal current conveyor (UCC) and the universal voltage conveyor (UVC), respectively, were designed at the Department of Telecommunication, BUT, Brno, and produced in cooperation with AMI Semiconductor Czech, Ltd. There is still the need to develop new active elements that offer new advantages. The main contribution of this thesis is, therefore, the definition of other novel ABBs such as the differential-input buffered and transconductance amplifier (DBTA), the current follower transconductance amplifier (CFTA), the z-copy current-controlled current inverting transconductance amplifier (ZC-CCCITA), the generalized current follower differential input transconductance amplifier (GCFDITA), the voltage gain-controlled modified current-feedback operational amplifier (VGC-MCFOA), and the minus-type current-controlled third-generation voltage conveyor (CC-VCIII-). Using the proposed ABBs, novel structures of first-order all-pass filters, second-order universal filters, KHN-equivalent circuits, inverse filters, active grounded inductance simulators, and quadrature sinusoidal oscillators working in the current-, voltage-, or mixed-mode are presented. The behavior of the proposed circuits has been verified by SPICE simulations and in selected cases also by experimental measurements.

Output-capacitorless low-dropout regulator for power management applications

This article aims to present the design of a 4.5-V, 450-mA low drop-out (LDO) voltage linear regulator based on a two-stage cascoded operational transconductance amplifier (OTA) as error amplifier. The aforementioned two-stage OTA is designed with cascoded current mirroring technique to boost up the output impedance. The proposed OTA has a DC gain of 101 dB under no load condition. The designed reference voltage included in the LDO regulator is provided by a band gap reference with the temperature coefficient (T¿) of 0.025 mV/ºC. The proposed LDO regulator has a maximum drop-out voltage of 0.5 V @ 450 mA of load current, and has the worst case power supply rejection ratio (PSRR) of [54.5 dB, 34.3 dB] @ [100 Hz, 10 kHz] in full load condition. All the proposed circuits are designed using a 0.35 µm CMOS technology. The design is checked in order to corroborate its performance for wide range of input voltage, founding that the circuit design works fine meeting all the initial specification requirements.Postprint (published version

Design of an output-capacitorless low-dropout regulator for power management applications

This article aims to present the design of a 4.5-V, 450-mA low drop-out (LDO) voltage linear regulator based on a twostage cascoded operational transconductance amplifier (OTA) as error amplifier. The aforementioned two-stage OTA is designed with cascoded current mirroring technique to boost up the output impedance. The proposed OTA has a DC gain of 101 dB under no load condition. The designed reference voltage included in the LDO regulator is provided by a band gap reference with the temperature coefficient (T¿) of 0.025 mV/ºC. The proposed LDO regulator has a maximum drop-out voltage of 0.5 V @ 450 mA of load current, and has the worst case power supply rejection ratio (PSRR) of [54.5 dB, 34.3 dB] @ [100 Hz, 10 kHz] in full load condition. All the proposed circuits are designed using a 0.35 µm CMOS technology. The design is checked in order to corroborate its performance for wide range of input voltage, founding that the circuit design works fine meeting all the initial specification requirements.Postprint (published version