Low-voltage current-mode CMOS filter structure for high frequency applications

Ankara : Department of Electrical and Electronics Engineering and the Institute of Engineering and Sciences of Bilkent University, 1995.Thesis (Master's) -- Bilkent University, 1995.Includes bibliographical references leaves 49-50.In this thesis, a new method for the design of tunable current-mode CMOS filters is presented. The proposed structure is suitable for low-voltage (3V) and high frequency applications. Basic building blocks are differential damped integrator and differential damped differentiator, which have tunable comer frequencies. Using first order building blocks and applying feedback techniques, biquadratic sections of low-pass, high-pass and band-pass filters are generated. Higher order filters are implemented by using cascaded biquad synthesis. Filters are tuned by means of two control voltages, from 50% to 130% of their corner frequencies. HSPICE simulations show that filter implementation up to 0.5GHz is possible for 2.4^ CMOS technology. The available frequency range can be increased using a better technology such as 0.7/i CMOS. Layouts for two test chips are generated using CADENCE full-custom design environment for 0.7/i and 2.4/i CMOS processes.Karşılayan, Aydın İlkerM.S

ON DESIGN OF SELF-TUNING ACTIVE FILTERS

In this paper, we present one approach in design of self-tuning all-pass, band-pass, low-pass and notch filters based on phase control loops with voltage-controlled active components and analyze their stability as well. The main idea is to vary signal delay of the filter and in this way to achieve phase correction. The filter phase characteristics are tuned by varying the transconductance of the operational transconductance amplifier or capacitance of an MOS varicap element, which are the constituents of filters. This approach allows us to implement active filters with capacitance values of order of pF, making the complete filter circuit to be amenable for realization in CMOS technology. The phase control loops are characterized by good controllable delay over the full range of phase and frequency regulation, high stability, and short settling (locking) time. The proposed circuits are suitable for implementation as a basic building RF function block, used in phase and frequency regulation, frequency synthesis, clock generation recovery, filtering, selective amplifying etc

Automatic tuning of continuous-time filters

Integrated high-Q continuous-time filters require adaptive tuning circuits that will correct the filter parameters such as center frequency and quality factor (Q). Three different automatic tuning techniques are introduced. In all of the proposed methods, frequencyand quality factor tuning loops are controlled digitally, providing stable tuning by activating only one loop at a given time. In addition, a direct relationship between passband gain and quality factor is not required, so the techniques can be applied to active LC filters as well as Gm-C filters. The digital-tuning method based on phase comparison was verified with 1% tuning accuracy at 5.5 MHz for Q of 20. It uses phase information for both Q and center-frequency tuning. The filter output phase is tuned to the known references, which are generated by a frequency synthesizer. The core tuning circuit consists of D flip-flops (DFF) and simple logic gates. DFFs are utilized to perform binary phase comparisons. The second method, high-order digital tuning based on phase comparison, is an extension of the previous technique to high-order analog filters without depending on the master-slave approach. Direct tuning of the overall filter response is achieved without separating individual biquad sections, eliminating switches and their parasitics. The tuning system was verified with a prototype 6th order bandpass filter at 19 MHz with 0.6 MHz bandwidth, which was fabricated in a conventional 0.5 [mu]m CMOS technology. Analysis of different practical limitations is also provided. Finally, the digital-tuning method based on magnitude comparison is proposed for second-order filters for higher frequency operations. It incorporates a frequency synthesizer to generate reference signals, an envelope detector and a switched comparator to compare output magnitudes at three reference frequencies. The theoretical analysis of the technique and the simulation results are provided

A programmable BiCMOS transconductance-capacitor filter for high frequencies

With advancements in CMOS technology, high speed analog circuits that were traditionally implemented with discrete circuit components can now be made monolithically. Antialiasing filters for video signals as well as signal conditioning filters in high speed communication channels are examples of applications where high frequency integrated circuits are now feasible. Transconductance-Capacitor or Gm-C filters are well suited to these applications as they operate in the continuous-time domain and are able to overcome the high-frequency and noise limitations imposed by clocked filter topologies. This thesis covers the design of a programmable fourth-order Chebychev filter with a 50MHz passband using the transconductance-C technique. A previously proposed transconductor based upon a CMOS inverter is used to implement the filter. Since this transconductor has no internal nodes, it can achieve extremely high bandwidths. However, it requires a variable power source for programming. Thus, a wide-band, on-chip, variable-BiCMOS power supply is presented as the method for setting the transconductance. Practical design issues are addressed as well as many methods for compensating non-idealities. Simulations of the filter as well as some parametric measurement of the filter structures are presented

High performance RF and baseband building blocks for wireless receivers

Because of the unique architecture of wireless receivers, a designer must understand both the high frequency aspects as well as the low-frequency analog considerations for different building blocks of the receiver. The primary goal of this research work is to explore techniques for implementing high performance RF and baseband building blocks for wireless applications. Several novel techniques to improve the performance of analog building blocks are presented. An enhanced technique to couple two LC resonators is presented which does not degrade the loaded quality factor of the resonators which results in an increased dynamic range. A novel technique to automatically tune the quality factor of LC resonators is presented. The proposed scheme is stable and fast and allows programming both the quality factor and amplitude response of the LC filter. To keep the oscillation amplitude of LC VCOs constant and thus achieving a minimum phase noise and a reliable startup, a stable amplitude control loop is presented. The proposed scheme has been also used in a master-slave quality factor tuning of LC filters. An efficient and low-cost architecture for a 3.1GHz-10.6GHz ultra-wide band frequency synthesizer is presented. The proposed scheme is capable of generating 14A novel pseudo-differential transconductance amplifier is presented. The proposed scheme takes advantage of the second-order harmonic available at the output current of pseudo-differential structure to cancel the third-order harmonic distortion. A novel nonlinear function is proposed which inherently removes the third and the fifth order harmonics at its output signal. The proposed nonlinear block is used in a bandpass-based oscillator to generate a highly linear sinusoidal output. Finally, a linearized BiCMOS transconductance amplifier is presented. This transconductance is used to build a third-order linear phase low pass filter with a cut-off frequency of 264MHz for an ultra-wide band receiver. carrier frequencies

Design of Highly linear Gm-C Low Pass and Complex Band Pass Filter for High Frequency Application

The present work deals with the design of low pass filters such as 3rd order Gm-C filter, a duty cycle controlled low pass and a complex band pass filter that can be operated for high frequency applications. The linearity and power consumption of a CMOS Gm-C filter are studied and optimized. Firstly, a doubly terminated 3rd order low-pass Gm-C filter is designed

Realization of Integrable Low- Voltage Companding Filters for Portable System Applications

Undoubtedly, today’s integrated electronic systems owe their remarkable performance primarily to the rapid advancements of digital technology since 1970s. The various important advantages of digital circuits are: its abstraction from the physical details of the actual circuit implementation, its comparative insensitiveness to variations in the manufacturing process, and the operating conditions besides allowing functional complexity that would not be possible using analog technology. As a result, digital circuits usually offer a more robust behaviour than their analog counterparts, though often with area, power and speed drawbacks. Due to these and other benefits, analog functionality has increasingly been replaced by digital implementations. In spite of the advantages discussed above, analog components are far from obsolete and continue to be key components of modern electronic systems. There is a definite trend toward persistent and ubiquitous use of analog electronic circuits in day-to-day life. Portable electronic gadgets, wireless communications and the widespread application of RF tags are just a few examples of contemporary developments. While all of these electronic systems are based on digital circuitry, they heavily rely on analog components as interfaces to the real world. In fact, many modern designs combine powerful digital systems and complementary analog components on a single chip for cost and reliability reasons. Unfortunately, the design of such systems-on-chip (SOC) suffers from the vastly different design styles of analog and digital components. While mature synthesis tools are readily available for digital designs, there is hardly any such support for analog designers apart from wellestablished PSPICE-like circuit simulators. Consequently, though the analog part usually occupies only a small fraction of the entire die area of an SOC, but its design often constitutes a major bottleneck within the entire development process. Integrated continuous-time active filters are the class of continuous-time or analog circuits which are used in various applications like channel selection in radios, anti-aliasing before sampling, and hearing aids etc. One of the figures of merit of a filter is the dynamic range; this is the ratio of the largest to the smallest signal that can be applied at the input of the filter while maintaining certain specified performance. The dynamic range required in the filter varies with the application and is decided by the variation in strength of the desired signal as well as that of unwanted signals that are to be rejected by the filter. It is well known that the power dissipation and the capacitor area of an integrated active filter increases in proportion to its dynamic range. This situation is incompatible with the needs of integrated systems, especially battery operated ones. In addition to this fundamental dependence of power dissipation on dynamic range, the design of integrated active filters is further complicated by the reduction of supply voltage of integrated circuits imposed by the scaling down of technologies to attain twin objective of higher speed and lower power consumption in digital circuits. The reduction in power consumption with decreasing supply voltage does not apply to analog circuits. In fact, considerable innovation is required with a reduced supply voltage even to avoid increasing power consumption for a given signal to noise ratio (S/N). These aspects pose a great hurdle to the active filter designer. A technique which has attracted the attention of circuit designers as a possible route to filters with higher dynamic range per unit power consumption is “companding”. Companding (compression-expansion) filters are a very promising subclass of continuous-time analog filters, where the input (linear) signal is initially compressed before it will be handled by the core (non-linear) system. In order to preserve the linear operation of the whole system, the non-linear signal produced by the core system is converted back to a linear output signal by employing an appropriate output stage. The required compression and expansion operations are performed by employing bipolar transistors in active region or MOS transistors in weak inversion; the systems thus derived are known as logarithmic-domain (logdomain) systems. In case MOS transistors operated in saturation region are employed, the derived structures are known as Square-root domain systems. Finally, the third class of companding filters can also be obtained by employing bipolar transistors in active region or MOS transistors in weak inversion; the derived systems are known as Sinh-domain systems. During the last several years, a significant research effort has been already carried out in the area of companding circuits. This is due to the fact that their main advantages are the capability for operation in low-voltage environment and large dynamic range originated from their companding nature, electronic tunability of the frequency characteristics, absence of resistors and the potential for operations in varied frequency regions.Thus, it is obvious that companding filters can be employed for implementing high-performance analog signal processing in diverse frequency ranges. For example, companding filters could be used for realizing subsystems in: xDSL modems, disk drive read channels, biomedical electronics, Bluetooth/ZigBee applications, phaselocked loops, FM stereo demodulator, touch-tone telephone tone decoder and crossover network used in a three-way high-fidelity loudspeaker etc. A number of design methods for companding filters and their building blocks have been introduced in the literature. Most of the proposed filter structures operate either above 1.5V or under symmetrical (1.5V) power supplies. According to data that provides information about the near future of semiconductor technology, International Technology Roadmap for Semiconductors (ITRS), in 2013, the supply voltage of digital circuits in 32 nm technology will be 0.5 V. Therefore, the trend for the implementation of analog integrated circuits is the usage of low-voltage building blocks that use a single 0.5-1.5V power supply. Therefore, the present investigation was primarily concerned with the study and design of low voltage and low power Companding filters. The work includes the study about: the building blocks required in implementing low voltage and low power Companding filters; the techniques used to realize low voltage and low power Companding filters and their various areas of application. Various novel low voltage and low power Companding filter designs have been developed and studied for their characteristics to be applied in a particular portable area of application. The developed designs include the N-th order universal Companding filter designs, which have been reported first time in the open literature. Further, an endeavor has been made to design Companding filters with orthogonal tuning of performance parameters so that the designs can be simultaneously used for various features. The salient features of each of the developed circuit are described. Electronic tunability is one of the major features of all of the designs. Use of grounded capacitors and resistorless designs in all the cases makes the designs suitable for IC technology. All the designs operate in a low-voltage and low-power environment essential for portable system applications. Unless specified otherwise, all the investigations on these designs are based on the PSPICE simulations using model parameters of the NR100N bipolar transistors and BSIM 0.35μm/TSMC 0.25μm /TSMC 0.18μm CMOS process MOS transistors. The performance of each circuit has been validated by comparing the characteristics obtained using simulation with the results present in the open literature. The proposed designs could not be realized in silicon due to non-availability of foundry facility at the place of study. An effort has already been started to realize some of the designs in silicon and check their applicability in practical circuits. At the basic level, one of the proposed Companding filter designs was implemented using the commercially available transistor array ICs (LM3046N) and was found to verify the theoretical predictions obtained from the simulation results

Design of Highly Efficient Analog-To-Digital Converters

The demand of higher data rates in communication systems is reflected in the constant evolution of communication standards. LTE-A and WiFi 802.11ac promote the use of carrier aggregation to increase the data rate of a wireless receiver. Recent DTV receivers promote the concept of full band capture to avoid the implementation of complex analog operations such as: filtering, equalization, modulation/demodulation, etc. All these operations can be implemented in a robust manner in the digital domain. Analog-to-Digital Converters (ADCs) are located at the heart of such architectures and require to have larger bandwidths and higher dynamic ranges. However, at higher data rates the power efficiency of ADCs tends to degrade. Moreover, while the scale of channel length in CMOS devices directly benefits the power, speed and area of digital circuits, analog circuits suffer from lower intrinsic gain and higher device mismatch. Thus, it has been difficult to design high-speed ADCs with low-power operation using traditional architectures without relying on increasingly complex digital calibration algorithms. This research presents three ADCs that introduce novel architectures to relax the specifications of the analog circuits and reduce the complexity of the digital calibration algorithms. A low-pass sigma delta ADC with 15 MHz of bandwidth is introduced. The system uses a low-power 7-bit quantizer from which the four most significant bits are used for the operation of the sigma delta ADC. The remaining three least significant bits are used for the realization of a frequency domain algorithm for quantization noise improvement. The prototype was implemented in 130 nm CMOS technology. For this prototype, the use of the 7-bit quantizer and algorithm improved the SNDR from 69 dB to 75 dB. The obtained FoM was 145 fJ/conversion-step. In a second project, the problem of high power consumption demanded from closed loop operational amplifiers operating at Giga hertz frequency is addressed. Especially the dependency of the power consumption to the closed loop gain. This project presents a low-pass sigma delta ADC with 75 MHz bandwidth. The traditional summing amplifier used for excess loop compensation delay is substituted by a summing amplifier with current buffer that decouples the power consumption dependency with the closed loop gain. The prototype was designed in 40 nm CMOS technology achieving 64.9 dB peak SNDR. The operating frequency was 3.2 GHz, the total power consumption was 22 mW and FoM of 106 fJ/conversion-step. In a third project, the same approach of decoupling the power consumption requirements from the closed loop gain is applied to a pipelined ADC. The traditional capacitive multiplying DAC used in the residual amplifier is substituted by a current mode DAC and a transimpedance amplifier. The prototype was implemented in 40 nm CMOS technology achieving 58 dB peak SNDR and 76 dB SFDR with 200 MHz sampling frequency. The ADC consumes 8.4 mW with a FoM of 64 fJ/Conversion-step