NASA Space Engineering Research Center for VLSI System Design

This annual report outlines the activities of the past year at the NASA SERC on VLSI Design. Highlights for this year include the following: a significant breakthrough was achieved in utilizing commercial IC foundries for producing flight electronics; the first two flight qualified chips were designed, fabricated, and tested and are now being delivered into NASA flight systems; and a new technology transfer mechanism has been established to transfer VLSI advances into NASA and commercial systems

FIPBLOX: a graphical interactive design tool for FIPSOC

FIPSOC is a field programmable mixed-signal integrated device consisting of a Field Programmable Gate Array (FPGA), a set of programmable and interconnectable analog cells, and a microprocessor core which can run general purpose user programs, handle the dynamic reconfiguration of the programmable blocks and probe, in real time, internal digital and analog signals. This device is specially suitable for development and fast prototyping of mixed signal integrated applications. As FIPSOC project is currently under development, it has no yet any powerful tool for synthesis and a structural VHDL (components) approach is to be used for designing. Therefore, the user starts from simple design structures and through a bottom-up style must build more complex components. In this paper we present FIPBLOX, a tool that allows the user automatically generate VHDL code for implementing and customizing high-level modules using the basic resources provided by the FIPSOC FPGA.Eje: Arquitectura, Redes y Sistemas Operativos (ARSO)Red de Universidades con Carreras en Informática (RedUNCI

The 1992 4th NASA SERC Symposium on VLSI Design

Papers from the fourth annual NASA Symposium on VLSI Design, co-sponsored by the IEEE, are presented. Each year this symposium is organized by the NASA Space Engineering Research Center (SERC) at the University of Idaho and is held in conjunction with a quarterly meeting of the NASA Data System Technology Working Group (DSTWG). One task of the DSTWG is to develop new electronic technologies that will meet next generation electronic data system needs. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The NASA SERC is proud to offer, at its fourth symposium on VLSI design, presentations by an outstanding set of individuals from national laboratories, the electronics industry, and universities. These speakers share insights into next generation advances that will serve as a basis for future VLSI design

Behavioral synthesis from VHDL using structured modeling

This dissertation describes work in behavioral synthesis involving the development of a VHDL Synthesis System VSS which accepts a VHDL behavioral input specification and performs technology independent synthesis to generate a circuit netlist of generic components. The VHDL language is used for input and output descriptions. An intermediate representation which incorporates signal typing and component attributes simplifies compilation and facilitates design optimization.A Structured Modeling methodology has been developed to suggest standard VHDL modeling practices for synthesis. Structured modeling provides recommendations for the use of available VHDL description styles so that optimal designs will be synthesized.A design composed of generic components is synthesized from the input description through a process of Graph Compilation, Graph Criticism, and Design Compilation. Experiments were performed to demonstrate the effects of different modeling styles on the quality of the design produced by VSS. Several alternative VHDL models were examined for each benchmark, illustrating the improvements in design quality achieved when Structured Modeling guidelines were followed

Modeling relays for power system protection studies

Numerical relays are the result of the application of microprocessor technology in relay industry. Numerical relays have the ability to communicate with its peers, are economical and are easy to operate, adjust and repair. Modeling of digital and numerical relays is important to adjust and settle protection equipment in electrical facilities and to train protection personnel. Designing of numerical relays is employed to produce new prototypes and protection algorithms. Computer models of numerical relays for the study of protection systems are greatly enhanced when working along with an electromagnetic transient program (emtp). A literature survey has revealed that previous modeling techniques presented a lack of automation in the generation of relay models, or show high complexity in linking the numerical relay models with the power system modeled in the emtp. This thesis describes a new approach of modeling and designing of numerical relays. The proposed methodology employs a Visual C++-based program (PLSA) to obtain from the user the specifications of the relay to be designed, and to process this information to generate the FORTRAN code that represents the functional blocks of the relay. This generated code is incorporated in a PSCAD/EMTDC case using a resource called component, which facilitates the creation of user-custom models in PSCAD/EMTDC. Convenient electrical and logical signals are connected to the inputs and outputs of the PSCAD/EMTDC component. Further additions of digital relay models into the PSCAD/EMTDC case constitute the protection system model. The thesis describes a procedure for designing distance and differential relay models, but the methodology may be extended to design models of other relay elements. A number of protection system studies were performed with the structure created with the proposed methodology. Adjustment of distance and differential relays were studied. Relay performance under CT saturation and the effects of the removal of anti-aliasing analog filter were investigated. Local and remote backup distance protection of transmission lines was simulated. The adjustment of differential protection of power transformer to overcome the effects of inrush current was performed. Power transformer differential protection responses to internal and external faults were considered. Additionally, a set of tests were performed to investigate the consistency of the relay models generated with the proposed methodology. The results showed that the numerical relay models respond satisfactorily according with the expected results of the tests

ASC: A stream compiler for computing with FPGAs

Published versio

A vision for edge AI

Edge Artificial Intelligence is progressively pervading all aspects of our life. However, to perform complex tasks, a massive amount of matrix multiplications needs to be computed. At the same time, the available hardware resources for computation are highly limited. The pressing need for efficiency serves as the motivation for this dissertation. In this dissertation, we propose a vision for highly-resource constrained future intelligent systems that are comprised of robust Binarized Neural Networks operating with approximate memory and approximate computing units, while being able to be trained on the edge