Mencer, O

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

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ASC: A stream compiler for computing with FPGAs

O. Mencer

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ASC: a stream compiler for computing with FPGAs

Abstract—A stream compiler (ASC) for computing with field programmable gate arrays (FPGAs) emerges from the ambition to bridge the hardware-design productivity gap where the number of available transistors grows more rapidly than the productivity of very large scale integration (VLSI) and FPGA computer-aided-design (CAD) tools. ASC addresses this problem with a software-like programming interface to hardware design (FPGAs) while keeping the performance of hand-designed circuits at the same time. ASC improves productivity by letting the programmer op-timize the implementation on the algorithm level, the architecture level, the arithmetic level, and the gate level, all within the same C++ program. The increased productivity of ASC is applied to the hardware acceleration of a wide range of applications. Traditionally, hard-ware accelerators are tediously handcrafted to achieve top per-formance. ASC simplifies design-space exploration of hardware accelerators by transforming the hardware-design task into a soft-ware-design process, using only “GNU compiler collection (GCC)” and “make ” to obtain a hardware netlist. From experience, the hardware-design productivity and ease of use are close to pure software development. This paper presents results and case studies with optimizations that are: 1) on the gate level—Kasumi and International Data Encryption Algorithm (IDEA) encryptions; 2) on the arithmetic level—redundant addition and multiplication function evaluation for two-dimensional (2-D) rotation; and 3) on the architecture level—Wavelet and Lempel–Ziv (LZ)-like compression. Index Terms—Design space exploration, FPGAs, hardware design. I

Oskar Mencer

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https://spiral.imperial.ac.uk/bitstream/10044/1/801/1/ASC

ASC: A stream compiler for computing with FPGAs

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