Design of Energy-Efficient A/D Converters with Partial Embedded Equalization for High-Speed Wireline Receiver Applications

As the data rates of wireline communication links increases, channel impairments such as skin effect, dielectric loss, fiber dispersion, reflections and cross-talk become more pronounced. This warrants more interest in analog-to-digital converter (ADC)-based serial link receivers, as they allow for more complex and flexible back-end digital signal processing (DSP) relative to binary or mixed-signal receivers. Utilizing this back-end DSP allows for complex digital equalization and more bandwidth-efficient modulation schemes, while also displaying reduced process/voltage/temperature (PVT) sensitivity. Furthermore, these architectures offer straightforward design translation and can directly leverage the area and power scaling offered by new CMOS technology nodes. However, the power consumption of the ADC front-end and subsequent digital signal processing is a major issue. Embedding partial equalization inside the front-end ADC can potentially result in lowering the complexity of back-end DSP and/or decreasing the ADC resolution requirement, which results in a more energy-effcient receiver. This dissertation presents efficient implementations for multi-GS/s time-interleaved ADCs with partial embedded equalization. First prototype details a 6b 1.6GS/s ADC with a novel embedded redundant-cycle 1-tap DFE structure in 90nm CMOS. The other two prototypes explain more complex 6b 10GS/s ADCs with efficiently embedded feed-forward equalization (FFE) and decision feedback equalization (DFE) in 65nm CMOS. Leveraging a time-interleaved successive approximation ADC architecture, new structures for embedded DFE and FFE are proposed with low power/area overhead. Measurement results over FR4 channels verify the effectiveness of proposed embedded equalization schemes. The comparison of fabricated prototypes against state-of-the-art general-purpose ADCs at similar speed/resolution range shows comparable performances, while the proposed architectures include embedded equalization as well

Design of High-Speed Power-Efficient A/D Converters for Wireline ADC-Based Receiver Applications

Serial input/output (I/O) data rates are increasing in order to support the explosion in network traffic driven by big data applications such as the Internet of Things (IoT), cloud computing and etc. As the high-speed data symbol times shrink, this results in an increased amount of inter-symbol interference (ISI) for transmission over both severe low-pass electrical channels and dispersive optical channels. This necessitates increased equalization complexity and consideration of advanced modulation schemes, such as four-level pulse amplitude modulation (PAM-4). Serial links which utilize an analog-to-digital converter (ADC) receiver front-end offer a potential solution, as they enable more powerful and flexible digital signal processing (DSP) for equalization and symbol detection and can easily support advanced modulation schemes. Moreover, the DSP back-end provides robustness to process, voltage, and temperature (PVT) variations, benefits from improved area and power with CMOS technology scaling and offers easy design transfer between different technology nodes and thus improved time-to-market. However, ADC-based receivers generally consume higher power relative to their mixed-signal counterparts because of the significant power consumed by conventional multi-GS/s ADC implementations. This motivates exploration of energy-efficient ADC designs with moderate resolution and very high sampling rates to support data rates at or above 50Gb/s. This dissertation presents two power-efficient designs of ≥25GS/s time-interleaved ADCs for ADC-based wireline receivers. The first prototype includes the implementation of a 6b 25GS/s time-interleaved multi-bit search ADC in 65nm CMOS with a soft-decision selection algorithm that provides redundancy for relaxed track-and-hold (T/H) settling and improved metastability tolerance, achieving a figure-of-merit (FoM) of 143fJ/conversion step and 1.76pJ/bit for a PAM-4 receiver design. The second prototype features the design of a 52Gb/s PAM-4 ADC-based receiver in 65nm CMOS, where the front-end consists of a 4-stage continuous-time linear equalizer (CTLE)/variable gain amplifier (VGA) and a 6b 26GS/s time-interleaved SAR ADC with a comparator-assisted 2b/stage structure for reduced digital-to-analog converter (DAC) complexity and a 3-tap embedded feed-forward equalizer (FFE) for relaxed ADC resolution requirement. The receiver front-end achieves an efficiency of 4.53bJ/bit, while compensating for up to 31dB loss with DSP and no transmitter (TX) equalization

Equalization Architectures for High Speed ADC-Based Serial I/O Receivers

The growth in worldwide network traffic due to the rise of cloud computing and wireless video consumption has required servers and routers to support increased serial I/O data rates over legacy channels with significant frequency-dependent attenuation. For these high-loss channel applications, ADC-based high-speed links are being considered due to their ability to enable powerful digital signal processing (DSP) algorithms for equalization and symbol detection. Relative to mixed-signal equalizers, digital implementations offer robustness to process, voltage and temperature (PVT) variations, are easier to reconfigure, and can leverage CMOS technology scaling in a straight-forward manner. Despite these advantages, ADC-based receivers are generally more complex and have higher power consumption relative to mixed-signal receivers. The ensuing digital equalization can also consume a significant amount of power which is comparable to the ADC contribution. Novel techniques to reduce complexity and improve power efficiency, both for the ADC and the subsequent digital equalization, are necessary. This dissertation presents efficient modeling and implementation approaches for ADC-based serial I/O receivers. A statistical modeling framework is developed, which is able to capture ADC related errors, including quantization noise, INL/DNL errors and time interleaving mismatch errors. A novel 10GS/s hybrid ADC-based receiver, which combines both embedded and digital equalization, is then presented. Leveraging a time-interleaved asynchronous successive approximation ADC architecture, a new structure for 3-tap embedded FFE inside the ADC with low power/area overhead is used. In addition, a dynamically-enabled digital 4-tap FFE + 3-tap DFE equalizer architecture is introduced, which uses reliable symbol detection to achieve remarkable savings in the digital equalization power. Measurement results over several FR4 channels verify the accuracy of the modeling approach and the effectiveness of the proposed receiver. The comparison of the fabricated prototype against state-of-the-art ADC-based receivers shows the ability of the proposed archi-tecture to compensate for the highest loss channel, while achieving the best power efficiency among other works

Modeling and Design of Architectures for High-Speed ADC-Based Serial Links

There is an ongoing dramatic rise in the volume of internet traffic. Standards such as 56Gb/s OIF very short reach (VSR), medium reach (MR) and long reach (LR) standards for chip to chip communication over channels with up to 10dB, 20dB and 30dB insertion loss at the PAM 4 Nyquist frequency, respectively, are being adopted. These standards call for the spectrally efficient PAM-4 signaling over NRZ signaling. PAM-4 signaling offers challenges such as a reduced SNR at the receiver, susceptibility to nonlinearities and increased sensitivity to residual ISI. Equalization provided by traditional mixed signal architectures can be insufficient to achieve the target BER requirements for very long reach channels. ADC-based receiver architectures for PAM-4 links take advantage of the more powerful equalization techniques, which lend themselves to easier and robust digital implementations, to extend the amount of insertion loss that the receiver can handle. However, ADC-based receivers can consume more power compared to mixed-signal implementations. Techniques that model the receiver performance to understand the various system trade-offs are necessary. This research presents a fast and accurate hybrid modeling framework to efficiently investigate system trade-offs for an ADC-based receiver. The key contribution being the addition of ADC related non-idealities such as quantization noise in the presence of integral and differential nonlinearities, and time-interleaving mismatch errors such as gain mismatch, bandwidth mismatch, offset mismatch and sampling skew. The research also presents a 52Gb/s ADC-based PAM-4 receiver prototype employing a 32-way time-interleaved, 2-bit/stage, 6-bit SAR ADC and a DSP with a 12-tap FFE and a 2-tap DFE. A new DFE architecture that reduces the complexity of a PAM-4 DFE to that of an NRZ DFE while simultaneously nearly doubling the maximum achievable data rate is presented. The receiver architecture also includes an analog front-end (AFE) consisting of a programmable two stage CTLE. A digital baud-rate CDR’s utilizing a Mueller-Muller phase detector sets the sampling phase. Measurement results show that for 32Gb/s operation a BER < 10⁻⁹ is achieved for a 30dB loss channel while for 52 Gb/s operation achieves a BER < 10⁻⁶ for a 31dB loss channel with a power efficiency of 8.06pj/bit

Design Techniques for High Performance Wireline Communication and Security Systems

As the amount of data traffic grows exponentially on the internet, towards thousands of exabytes by 2020, high performance and high efficiency communication and security solutions are constantly in high demand, calling for innovative solutions. Within server communication dominates todays network data transfer, outweighing between-server and server-to-user data transfer by an order of magnitude. Solutions for within-server communication tend to be very wideband, i.e. on the order of tens of gigahertz, equalizers are widely deployed to provide extended bandwidth at reasonable cost. However, using equalizers typically costs the available signal-to-noise ratio (SNR) at the receiver side. What is worse is that the SNR available at the channel becomes worse as data rate increases, making it harder to meet the tight constraint on error rate, delay, and power consumption. In this thesis, two equalization solutions that address optimal equalizer implementations are discussed. One is a low-power high-speed maximum likelihood sequence detection (MLSD) that achieves record energy efficiency, below 10 pico-Joule per bit. The other one is a phase-shaping equalizer design that suppresses inter-symbol interference at almost zero cost of SNR. The growing amount of communication use also challenges the design of security subsystems, and the emerging need for post-quantum security adds to the difficulties. Most of currently deployed cryptographic primitives rely on the hardness of discrete logarithms that could potentially be solved efficiently with a powerful enough quantum computer. Efficient post-quantum encryption solutions have become of substantial value. In this thesis a fast and efficient lattice encryption application-specific integrated circuit is presented that surpasses the energy efficiency of embedded processors by 4 orders of magnitude.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/146092/1/shisong_1.pd

A Maximum Likelihood Sequence Equalizing Architecture Using Viterbi Algorithm for ADC-Based Serial Link

Channel impairments in high data rates make Analog-to-digital (ADC) serial link a very attractive choice in terms of bandwidth efficient modulation; however, power limitation of these receivers make the ADC front-end design rather challenging [3]. By replacing traditional symbol by-symbol digital equalizer with a maximum likelihood sequence estimator (MLSE) receiver, in ADC serial link, we can produce a more optimal equalizing architecture in terms of noise, and simplify the complexity of the design in the analog front-end [7]. MLSE architecture is implemented using the Viterbi algorithm, in Matlab, and the parameters for the analog front-end circuits were defined by plotting the bit error rate (BER) as a function of different SNRs. Comparing the BER between the traditionally used MMSE equalizer and MLSE receiver BER was found to be lower for same SNR. Although using the Viterbi algorithm to determine the original signal sequence may make MLSE computationally challenging, the simplicity of analog front-end and lower BER makes this an effective choice for high bandwidth transmission in a digital-heavy receiver

Design of energy efficient high speed I/O interfaces

Energy efficiency has become a key performance metric for wireline high speed I/O interfaces. Consequently, design of low power I/O interfaces has garnered large interest that has mostly been focused on active power reduction techniques at peak data rate. In practice, most systems exhibit a wide range of data transfer patterns. As a result, low energy per bit operation at peak data rate does not necessarily translate to overall low energy operation. Therefore, I/O interfaces that can scale their power consumption with data rate requirement are desirable. Rapid on-off I/O interfaces have a potential to scale power with data rate requirements without severely affecting either latency or the throughput of the I/O interface. In this work, we explore circuit techniques for designing rapid on-off high speed wireline I/O interfaces and digital fractional-N PLLs. A burst-mode transmitter suitable for rapid on-off I/O interfaces is presented that achieves 6 ns turn-on time by utilizing a fast frequency settling ring oscillator in digital multiplying delay-locked loop and a rapid on-off biasing scheme for current mode output driver. Fabricated in 90 nm CMOS process, the prototype achieves 2.29 mW/Gb/s energy efficiency at peak data rate of 8 Gb/s. A 125X (8 Gb/s to 64 Mb/s) change in effective data rate results in 67X (18.29 mW to 0.27 mW) change in transmitter power consumption corresponding to only 2X (2.29 mW/Gb/s to 4.24 mW/Gb/s) degradation in energy efficiency for 32-byte long data bursts. We also present an analytical bit error rate (BER) computation technique for this transmitter under rapid on-off operation, which uses MDLL settling measurement data in conjunction with always-on transmitter measurements. This technique indicates that the BER bathtub width for 10^(−12) BER is 0.65 UI and 0.72 UI during rapid on-off operation and always-on operation, respectively. Next, a pulse response estimation-based technique is proposed enabling burst-mode operation for baud-rate sampling receivers that operate over high loss channels. Such receivers typically employ discrete time equalization to combat inter-symbol interference. Implementation details are provided for a receiver chip, fabricated in 65nm CMOS technology, that demonstrates efficacy of the proposed technique. A low complexity pulse response estimation technique is also presented for low power receivers that do not employ discrete time equalizers. We also present techniques for implementation of highly digital fractional-N PLL employing a phase interpolator based fractional divider to improve the quantization noise shaping properties of a 1-bit ∆Σ frequency-to-digital converter. Fabricated in 65nm CMOS process, the prototype calibration-free fractional-N Type-II PLL employs the proposed frequency-to-digital converter in place of a high resolution time-to-digital converter and achieves 848 fs rms integrated jitter (1 kHz-30 MHz) and -101 dBc/Hz in-band phase noise while generating 5.054 GHz output from 31.25 MHz input

8-bit 1 Gs/s Adc Architecture And 4-bit Flash Adc For +10 Gs/s Time Interleaved Adc In 65nm Cmos Technology

Tez (Yüksek Lisans) -- İstanbul Teknik Üniversitesi, Fen Bilimleri Enstitüsü, 2015Thesis (M.Sc.) -- İstanbul Technical University, Instıtute of Science and Technology, 2015Haberleşme sistemlerinin veri aktarım sıklıkları ve bant genişlikleri sürekli olarak artmaktadır. Sayısal yarıiletken teknolojilerindeki gelişmeler, haberleşme sistemlerindeki işaret işleme kısımlarını sayısal domenine almıştır. Sayısal işaret işlemenin avantajları, ideal olmayan durumlara yüksek tolerans, gerçekleme kolaylığı, bir fonksiyonu gerçeklemek için gereken alanın dolayısıyla maliyetin düşük olması ve yeni teknolojilere taşınabilme olarak sayılabilir. Bu avantajlardan faydalanmak için analog işaretleri sayısal domene almada köprü görevi görecek yüksek hızlı analog-sayısal dönüştürücülere(ADC) ihtiyaç vardır. Kablolu ve kablosuz haberleşme teknolojilerinde 10 GHz'yi de aşan bant genişlikleri tek kanallı ADCleri bu iş için elverişsiz kılmaktadır. Zaman aralıklı ADCler gerek ulaşabilecekleri dönüştürme hızı gerek güç verimliliği açısından iyi bir aday olarak karşımıza çıkar. Zaman aralıklama, tek kanallı eş ADClerin sıra ile kullanılması esasına dayanmaktadır. Sıradaki örneği alan ADC, sıra tekrar kendisine gelene kadar bu örneği dönüştürür. Dolayısıyla toplam dönüştürme hızı, tek bir dönüştürücünün hızı ile kanal sayısının çarpımı kadar olmaktadır. Bu şekilde yüksek dönüştürme hızları elde edilebilir. Ayrıca bu şekilde tek kanal ADCler daha fazla hız elde etmek için güç bakımından verimsiz oldukları noktalara itilmez ve daha verimli yapılar ortaya çıkar. Zaman aralıklı ADClerdeki kanal uyumsuzlukları performansı düşürmektedir. Bu hatalar temel olarak dengesizlik, kazanç ve zamanlama uyumsuzluklarından ileri gelmektedir. Zamanlama hataları kestirilmeleri ve düzeltilmeleri noktasında diğerlerinden daha zorludur ve bu durum yüksek frekanslarda daha da zorlaşmaktadır. Zaman aralıklı ADClerdeki zamanlama hatalarının kestirilmeleri ve düzeltilmeleri güncel bir araştırma konusu teşkil etmektedir. Hataların kalibrasyonu ön planda veya arka planda yapılabilir. Arka planda yapılan kalibrasyon sistemin işlerliği ile ilgili herhangi bir sıkıntı yaratmaması ve değişen çevre şartlarına uyum sağlayabilme esnekliği açısından daha avantajlıdır. Zaman aralıklama hataları frekans spektrumunda çıkıntılar(spur) oluşturmaktadır. Bu çıkıntılar, güçlü olmaları durumunda alıcı kısmındaki devreleri sıkıştırma noktasına iterek modülasyonlu işaretlerin sezilmesini zorlaştırabilir veya giriş işaretini tamamen engelleyebilirler. Dolayısıyla kanal uyumsuzluk hataları özellikle kablosuz haberleşme sistemleri için sorun teşkil etmektedir. Bu sorunlardan kurtulmak için kanalları rastgele kullanmaya dayanan bir teknik önerilmiştir. Bu teknik ile kanallardan kaynaklanan hatalar çıkışa rastgele bir sırayla etki yaptıklarından gürültü gibi bir karaktere geçerler. Dolayısıyla frekans spektrumundaki çıkıntılar söndürülmüş olur. Tekniğin bir diğer avantajı arka planda çalışmasıdır. Ancak dikkat edilmelidir ki bu teknik bir hata düzeltme tekniği değildir, dolayısıyla sistemin işaretgürültü oranını iyileştirmemektedir. Kanal uyumsuzluk hatalarının kestirilmesi gibi, saat işaretlerinin dağıtılması da artan kanal sayısı ile zorlaşmaktadır. Ayrıca yüksek kanal sayısına sahip olan zaman aralıklı ADClerde saat işareti dağıtımının tükettiği güç yüksek seviyelere ulaşabilir. Belli bir dönüştürme hızı için kanal sayısını düşük tutmak ise kanal ADClerinin dönüştürme hızlarını arttırmak ile mümkündür. ADClerin hızları yüksek tutulurken aynı zamanda güç verimliliği de yüksek tutulmalıdır. Bu hedefler doğrultusunda 8-bit 1 GS/s bir çevrimde birden fazla bit dönüştüren bir SAR ADC yapısı önerilmiştir. Bir çevrimde birden fazla bit dönüştüren SAR ADCler, tek kanalda yüksek hızlara çıkmak konusunda sıkça kullanılan bir yöntem olarak karşımıza çıkmaktadır. Bunun yanında ilk üç en anlamlı bit bir flash ADC ile dönüştürüldüğünden önemli hız kazanımları elde edilir. Flash ADC çıkışında bir kod çözücü yapısı kullanılmaması da zaman kazanımında etkilidir. Önerilen ADC yapısında özgün bir dönüştürme algoritması kullanılmaktadır. Algoritma temel olarak, dönüştürme fazlarına fazladan seviyeler eklemek ve fazların aralıklarını kesiştirmek sureti ile devre bloklarının hata toleranslarını arttırmasına dayanmaktadır. Bu nedenle herhangi bir kalibrasyon sistemine ihtiyaç duyulmaz dolayısıyla güç tüketimi azaltılabilir. Bu yapının gerçeklenebilmesi için çoklu seviye üreten bir ön kuvvetlendirici önerilmiştir. Önerilen ön kuvvetlendirici yapısı nedeniyle, algoritmadaki farklı fazlar için tek bir ön kuvvetlendirici kullanılabilmektedir. Bu sayede farklı ön kuvvetlendiricilerden kaynaklanacak dengesizlik uyumsuzluklarının da önüne geçilmiş olur. Yüksek hızlı veri dönüştürücülerin gerçeklenmesindeki en etkili devre bloğu, kendisi de 1 bitlik bir ADC olarak sayılabilecek karşılaştırıcı devreleridir. Karşılaştırıcı devresinin hızı, doğruluğu ve güç tüketimi bir ADCnin ilgili performans parametrelerini doğrudan etkilemektedir. Yüksek karşılaştırma hızlı özgün bir gömülü ön kuvvetlendiricili karşılaştırıcı devre önerilmiştir. Yapı geleneksel dinamik sezme kuvvetlendiricisi devresi temel alınarak tasarlanmıştır. Ek olarak giriş farksal kuvvetlendirici bölümüne bir statik akım kaynağı bağlanmıştır. Bu şekilde dinamik karşılaştırıcı yapısına ön kuvvetlendirici gömülmüş olur. Yapı geleneksel yapılara nazaran, hız, dengesizlik, güç tüketimi ve geri tepme gürültüsü açısından iyileştirmeler içermektedir. 8-bit 1 GS/s bir çevrimde birden fazla bit dönüştüren SAR ADC yapısı, ilk 3 biti olabildiğince hızlı dönüştürmek için bir flash ADC yapısı kullanmaktadır. Flash ADC yapılarının önemli hız avantajlarına rağmen, karşılaştırıcı devrelerin dengesizlik ve geri tepme gürültüsü performansı düşürmektedir. Önerilen gömülü ön kuvvetlendiricili karşılaştırıcı devresi dengesizlik performansını ve geri tepme gürültüsünü iyileştirmektedir. Ancak geri tepme gürültüsünden kaynaklanan hataları tam olarak çözmek adına, referans gerilimleri de giriş işaretleri gibi örneklenebilir. Bu teknik ile karşılaştırıcı geri tepme gürültüsünün giriş ve referans gerilimi üzerindeki etkisi eşitlenmekte ve geri tepme gürültüsünün etkisi bertaraf edilmektedir. ADC girişleri örneklenerek geldiğinden ve örnekleme devrelerindeki bir hata doğrudan ADCye iletileceğinden bu devrelerin performansı çok önemlidir. Çapraz bağlamalı anahtar tekniği kullanılarak anahtarların doğrusallığı iyileştirilmiştir. Aynı zamanda çapraz bağlama tekniği anahtar yük enjeksiyonu hatasını giriş işaretinden bağımsız hale getirmektedir. Bu durum, yukarıda bahsedilen referans örnekleme tekniği ile birleştirildiğinde flash ADC için önemli bir doğruluk iyileştirmesi sağlamaktadır. ADC blokları ST Microelectronics 65 nm CMOS teknolojisinde tasarlanmış ve serimleri yapılmıştır. Serim sonrası benzetim sonuçları tasarımların ve kullanılan tekniklerin doğruluğunu göstermektedir. Tasarlanan ADC Haziran 2015'de üretime yollanmıştır. Kasım 2015'de ölçümlere başlanması planlanmaktadır.Data rate of communication systems constantly increasing . Rapid scaling of digital semiconductor technologies has moved the signal processing of these systems to digital domain. Therefore high-speed ADCs are required to form the bridge to take the analog signals in digital domain. Data rates exceeding 10 Gbps makes the use of single channel ADCs unfeasible on this purpose. A power efficient solution is time-interleaving. Time-interleaving relaxes the speed requirements on single channel ADCs and lets designers to focus on power efficiency of the ADC. Channel mismatches in time-interleaved ADCs causes performance degradation. Errors arise mainly due to offset, gain and timing mismatch of channels. Among them, timing error is the most problematic since estimation of timing errors becomes more cumbersome in high-frequencies. Estimation and correction of timing errors in time-interleaved ADCs are hot topics of research. Calibration of errors can be on background or on foreground. Background calibration is more desirable since it allows system to adapt to changing conditions while not hindering the operation of the ADC. Time interleaving errors generate spurs on the spectrum. Spurs are problematic for the wireless communication systems, since they may block the input signal. In order to extinguish the spurs a channel randomization technique is proposed. Technique is based on randomly taking one of the ADC channels to make the errors of the channels noise-like term. It is advantageous since it works on background. Technique maintains a spur-free spectrum however does not improve the SNR of the system. Estimation of channel mismatch errors and clock distribution in a time-interleaved ADC becomes tedious as the number of channels increase. In order to keep the channel number low, channels should be fast while being power efficient. To satisfy this task, an 8-bit 1 GS/s multi-bit per cycle ADC is proposed. ADC employs a novel search algorithm based on redundancy. No calibration scheme required thanks to the algorithm therefore the power efficiency of the system can be increased. In order to realize the multi-bit per cycle structure, a multiple-threshold generation preamp is proposed. Comparators are the most important part of an ADC. Comparator specifications such as speed, accuracy and power consumption directly affect the relative specifications of the whole ADC. A novel latch with embedded preamp is proposed. Novel structure has latch regeneration time, offset, power consumption and kickback noise improvements over the conventional structures. 8-bit 1 GS/s multi-bit per cycle SAR ADC employs a flash ADC to perform the coarse conversion benefit from its speed. Although flash ADCs are fast, offset and kickback noise of comparators can penalize their accuracy. Proposed latch with embedded preamp improves the offset performance. To solve the kickback issue, reference voltages of the flash ADC are sampled. This technique is based on equalizing the kickback for both input and reference voltages therefore eliminating the effect. Sampling network of the ADC is critically important since any error made in the sampling phase directly passes to the ADC. Bootstrapped switches are used to improve the linearity of the switches. By using bootstrap switches, charge injection can be made signal independent. If it is combined with the reference sampling technique used in flash ADC, effects of charge injection can be diminished significantly. ADC blocks are designed and laid out in ST Microlectronics 65 nm process. Postlayout simulations have proven the efectiveness of the proposed techniques and blocks. Tape-out was done in July 2015. Measurements is expected to take place in November 2015.Yüksek LisansM.Sc

MIMO Systems

In recent years, it was realized that the MIMO communication systems seems to be inevitable in accelerated evolution of high data rates applications due to their potential to dramatically increase the spectral efficiency and simultaneously sending individual information to the corresponding users in wireless systems. This book, intends to provide highlights of the current research topics in the field of MIMO system, to offer a snapshot of the recent advances and major issues faced today by the researchers in the MIMO related areas. The book is written by specialists working in universities and research centers all over the world to cover the fundamental principles and main advanced topics on high data rates wireless communications systems over MIMO channels. Moreover, the book has the advantage of providing a collection of applications that are completely independent and self-contained; thus, the interested reader can choose any chapter and skip to another without losing continuity