There is an ongoing dramatic rise in the volume of internet traffic. Standards such as
56Gb/s OIF very short reach (VSR), medium reach (MR) and long reach (LR) standards for chip
to chip communication over channels with up to 10dB, 20dB and 30dB insertion loss at the PAM
4 Nyquist frequency, respectively, are being adopted. These standards call for the spectrally
efficient PAM-4 signaling over NRZ signaling. PAM-4 signaling offers challenges such as a
reduced SNR at the receiver, susceptibility to nonlinearities and increased sensitivity to residual
ISI. Equalization provided by traditional mixed signal architectures can be insufficient to achieve
the target BER requirements for very long reach channels. ADC-based receiver architectures for
PAM-4 links take advantage of the more powerful equalization techniques, which lend themselves
to easier and robust digital implementations, to extend the amount of insertion loss that the receiver
can handle. However, ADC-based receivers can consume more power compared to mixed-signal
implementations. Techniques that model the receiver performance to understand the various
system trade-offs are necessary.
This research presents a fast and accurate hybrid modeling framework to efficiently
investigate system trade-offs for an ADC-based receiver. The key contribution being the addition
of ADC related non-idealities such as quantization noise in the presence of integral and differential
nonlinearities, and time-interleaving mismatch errors such as gain mismatch, bandwidth
mismatch, offset mismatch and sampling skew.
The research also presents a 52Gb/s ADC-based PAM-4 receiver prototype employing
a 32-way time-interleaved, 2-bit/stage, 6-bit SAR ADC and a DSP with a 12-tap FFE and a 2-tap
DFE. A new DFE architecture that reduces the complexity of a PAM-4 DFE to that of an NRZ
DFE while simultaneously nearly doubling the maximum achievable data rate is presented. The
receiver architecture also includes an analog front-end (AFE) consisting of a programmable two
stage CTLE. A digital baud-rate CDR’s utilizing a Mueller-Muller phase detector sets the sampling
phase. Measurement results show that for 32Gb/s operation a BER < 10⁻⁹ is achieved for a 30dB
loss channel while for 52 Gb/s operation achieves a BER < 10⁻⁶ for a 31dB loss channel with a
power efficiency of 8.06pj/bit
