High Efficiency LED Drivers: A Review

Recently various soft switching techniques have been developed for various DC-DC based LED drivers. Typical driver circuits in the market have efficiency between 80% - 95% with majority having efficiency between 80% - 90%. Various topologies and strategies are available to obtain the best performance. A comparison and discussion of different buck and floating buck topologies used as driver in LED lighting application are presented in this paper

Miniaturized Low-Voltage Power Converters With Fast Dynamic Response

This paper demonstrates a two-stage approach for power conversion that combines the strengths of variable-topology switched capacitor techniques (small size and light-load performance) with the regulation capability of magnetic switch-mode power converters. The proposed approach takes advantage of the characteristics of complementary metal-oxide-semiconductor (CMOS) processes, and the resulting designs provide excellent efficiency and power density for low-voltage power conversion. These power converters can provide low-voltage outputs over a wide input voltage range with very fast dynamic response. Both design and fabrication considerations for highly integrated CMOS power converters using this architecture are addressed. The results are demonstrated in a 2.4-W dc-dc converter implemented in a 180-nm CMOS IC process and co-packaged with its passive components for high performance. The power converter operates from an input voltage of 2.7-5.5 V with an output voltage of ≤1.2 V, and achieves a 2210 W/in[superscript 3] power density with ≥80% efficiency.Focus Center Research ProgramUnited States. Defense Advanced Research Projects AgencySemiconductor Research CorporationCharles Stark Draper Laborator

Digital Controlled Multi-phase Buck Converter with Accurate Voltage and Current Control

abstract: A 4-phase, quasi-current-mode hysteretic buck converter with digital frequency synchronization, online comparator offset-calibration and digital current sharing control is presented. The switching frequency of the hysteretic converter is digitally synchronized to the input clock reference with less than ±1.5% error in the switching frequency range of 3-9.5MHz. The online offset calibration cancels the input-referred offset of the hysteretic comparator and enables ±1.1% voltage regulation accuracy. Maximum current-sharing error of ±3.6% is achieved by a duty-cycle-calibrated delay line based PWM generator, without affecting the phase synchronization timing sequence. In light load conditions, individual converter phases can be disabled, and the final stage power converter output stage is segmented for high efficiency. The DC-DC converter achieves 93% peak efficiency for Vi = 2V and Vo = 1.6V.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201

Merged Two-Stage Power Converter With Soft Charging Switched-Capacitor Stage in 180 nm CMOS

In this paper, we introduce a merged two-stage dc-dc power converter for low-voltage power delivery. By separating the transformation and regulation function of a dc-dc power converter into two stages, both large voltage transformation and high switching frequency can be achieved. We show how the switched-capacitor stage can operate under soft charging conditions by suitable control and integration (merging) of the two stages. This mode of operation enables improved efficiency and/or power density in the switched-capacitor stage. A 5-to-1 V, 0.8 W integrated dc-dc converter has been developed in 180 nm CMOS. The converter achieves a peak efficiency of 81%, with a regulation stage switching frequency of 10 MHz.Interconnect Focus Center (United States. Defense Advanced Research Projects Agency and Semiconductor Research Corporation

Dual-frequency single-inductor multiple-output (DF-SIMO) power converter topology for SoC applications

Modern mixed-signal SoCs integrate a large number of sub-systems in a single nanometer CMOS chip. Each sub-system typically requires its own independent and well-isolated power supply. However, to build these power supplies requires many large off-chip passive components, and thus the bill of material, the package pin count, and the printed circuit board area and complexity increase dramatically, leading to higher overall cost. Conventional (single-frequency) Single-Inductor Multiple-Output (SIMO) power converter topology can be employed to reduce the burden of off-chip inductors while producing a large number of outputs. However, this strategy requires even larger off-chip output capacitors than single-output converters due to time multiplexing between the multiple outputs, and thus many of them suffer from cross coupling issues that limit the isolation between the outputs. In this thesis, a Dual-Frequency SIMO (DF-SIMO) buck converter topology is proposed. Unlike conventional SIMO topologies, the DF-SIMO decouples the rate of power conversion at the input stage from the rate of power distribution at the output stage. Switching the input stage at low frequency (~2 MHz) simplifies its design in nanometer CMOS, especially with input voltages higher than 1.2 V, while switching the output stage at higher frequency enables faster output dynamic response, better cross-regulation, and smaller output capacitors without the efficiency and design complexity penalty of switching both the input and output stages at high frequency. Moreover, for output switching frequency higher than 100 MHz, the output capacitors can be small enough to be integrated on-chip. A 5-output 2-MHz/120-MHz design in 45-nm CMOS with 1.8-V input targeting low-power microcontrollers is presented as an application. The outputs vary from 0.6 to 1.6 V, with 4 outputs providing up to 15 mA and one output providing up to 50 mA. The design uses single 10-uH off-chip inductor, 2-nF on-chip capacitor for each 15-mA output and 4.5-nF for the 50-mA output. The peak efficiency is 73%, Dynamic Voltage Scaling (DVS) is 0.6 V/80 ns, and settling time is 30 ns for half-to-full load steps with no observable overshoot/undershoot or cross-coupling transients. The DF-SIMO topology enables realizing multiple efficient power supplies with faster dynamic response, better cross-regulation, and lower overall cost compared to conventional SIMO topologies

A New Mirroring Circuit for Power MOS Current Sensing Highly Immune to EMI

This paper deals with the monitoring of power transistor current subjected to radio-frequency interference. In particular, a new current sensor with no connection to the power transistor drain and with improved performance with respect to the existing current-sensing schemes is presented. The operation of the above mentioned current sensor is discussed referring to time-domain computer simulations. The susceptibility of the proposed circuit to radio-frequency interference is evaluated through time-domain computer simulations and the results are compared with those obtained for a conventional integrated current sensor

Modularizing the LDO to optimize performance based on application design constraints

This thesis aims to construct a modular low-dropout regulator that gives designers more freedom in building a highly efficient regulator that meets application demands. This modular design is able to separate DC regulation and high-frequency supply rejection while not compromising on either of the two. Flexibility is a key requirement during both design and post-design. The proposed regulator is able to achieve all the required goals with full spectrum power supply rejection. By splitting the pass device, this design is able to achieve the best of both internal pole dominant and external pole dominant linear regulators

Design of High Efficiency Brushless Permanent Magnet Machines and Driver System

The dissertation is concerned with the design of high-efficiency permanent magnet synchronous machinery and the control system. The dissertation first talks about the basic concept of the permanent magnet synchronous motor (PMSM) design and the mathematics design model of the advanced design method. The advantage of the design method is that it can increase the high load capacity at no cost of increasing the total machine size. After that, the control method of the PMSM and Permanent magnet synchronous generator (PMSG) is introduced. The design, simulation, and test of a permanent magnet brushless DC (BLDC) motor for electric impact wrench and new mechanical structure are first presented based on the design method. Finite element analysis based on the Maxwell 2D is built to optimize the design and the control board is designed using Altium Designer. Both the motor and control board have been fabricated and tested to verify the design. The electrical and mechanical design are combined, and it provides an analytical IPMBLDC design method and an innovative and reasonable mechanical dynamical calculation method for the impact wrench system, which can be used in whole system design of other functional electric tools. A 2kw high-efficiency alternator system and its control board system are also designed, analyzed and fabricated applying to the truck auxiliary power unit (APU). The alternator system has two stages. The first stage is that the alternator three-phase outputs are connected to the three-phase active rectifier to get 48V DC. An advanced Sliding Mode Observer (SMO) is used to get an alternator position. The buck is used for the second stage to get 14V DC output. The whole system efficiency is much higher than the traditional system using induction motor

Design and Development of a Multi-Purpose Input Output Controller Board for the SPES Control System

This PhD work has been carried out at the Legnaro National Laboratories (LNL), one of the four national labs of the National Institute for Nuclear Physics (INFN). The mission of LNL is to perform research in the field of nuclear physics and nuclear astrophysics together with emerging technologies. Technological research and innovation are the key to promote excellence in science, to excite competitive industries and to establish a better society. The research activities concerning electronics and computer science are an essential base to develop the control system of the Selective Production of Exotic Species (SPES) project. Nowadays, SPES is the most important project commissioned at LNL and represents the future of the Lab. It is a second generation Isotope Separation On-Line (ISOL) radioactive ion beam facility intended for fundamental nuclear physics research as well as experimental applications in different fields of science, such as nuclear medicine; radio-pharmaceutical production for therapy and diagnostic. The design of the SPES control system demands innovative technologies to embed the control of several appliances with different requirements and performing different tasks spanning from data sharing and visualization, data acquisition and storage, networking, security and surveillance operations, beam transport and diagnostic. The real time applications and fast peripherals control commonly found in the distributed control network of particle accelerators are accompanied by the challenge of developing custom embedded systems. In this context, the proposed PhD work describes the design and development of a multi-purpose Input Output Controller (IOC) board capable of embedding the control of typical accelerator instrumentation involved in the automatic beam transport system foreseen for the SPES project. The idea behind this work is to extend the control reach to the single device level without losing in modularity and standardization. The outcome of the research work is a general purpose embedded computer that will be the base for standardizing the hardware layer of the frontend computers in the SPES distributed control system. The IOC board is a Computer-on-Module (COM) carrier board designed to host any COM Express type 6 module and is equipped with a Field Programmable Gate Array (FPGA) and user application specific I/O connection solutions not found in a desktop pc. All the generic pc functionalities are readily available in off-the-shelf modules and the result is a custom motherboard that bridges the gap between custom developments and commercial personal computers. The end user can deal with a general-purpose pc with a high level of hardware abstraction besides being able to exploit the on-board FPGA potentialities in terms of fast peripherals control and real time digital data processing. This document opens with an introductory chapter about the SPES project and its control system architecture and technology before to describe the IOC board design, prototyping, and characterization. The thesis ends describing the installation in the field of the IOC board which is the core of the new diagnostics data readout and signal processing system. The results of the tests performed under real beam conditions prove that the new hardware extends the current sensitivity to the pA range, addressing the SPES requirements, and prove that the IOC board is a reliable solution to standardize the control of several appliances in the SPES accelerators complex where it will be embedded into physical equipment, or in their proximity, and will control and monitor their operation replacing the legacy VME technology. The installation in the field of the IOC board represents a great personal reward and crowns these years of busy time during which I turned what was just an idea in 2014, into a working embedded computer today