On the design of ultra low voltage CMOS oscillators.

Wireless sensor nodes require very tight power budgets to operate from either asmall battery, some energy harvesting mechanism or both. In many cases, thermalor electrochemical harvesting devices provide very low voltages of the order of100 mV or even lower. Time-keeping functionality is required in IoT systems andthe time-keeping module must be on at all times. Crystal oscillators have provento be useful for low power time-keeping applications, and in this context supplyvoltage lowering is a convenient strategy. Therefore, 32 kHz crystal oscillatorsoperating with only 60 mV supply are presented. Two implementations based ona Schmitt trigger circuit for two different crystals were designed and experimentallycharacterized.These crystal oscillators are based on the application of a Schmitt trigger asan amplifier. Guidelines for designing this block to be the amplifier of a crystaloscillator are provided. Furthermore, a dynamic model of the Schmitt trigger isproposed and the model results are compared against simulations. The amplifierswere experimentally characterized, providing a gain of 2.48 V/V with a 60 mVpower supply. As it was intended in the design stage, for voltages above 100 mVhysteresis appears and the Schmitt trigger starts operating as a comparator.The Schmitt triggers to operate as amplifiers of the crystal oscillators aredesigned in a 130 nm CMOS process, requiring an area of 45μm x 74μm and78μm x 83μm, respectively. The power consumptions of the crystal oscillators are2.26 nW and 15 nW and the temperature stabilities attained are 62 ppm (25-62°C)and 50 ppm (5-62°C), respectively. The dependence on the supply voltage of thecurrent consumption, fractional frequency, start-up time and oscillation amplitudewere measured. The Allan deviation is 30 ppb for both oscillators.On the other hand, an LC voltage controlled oscillator (VCO) is designed in28 nm FD-SOI for RF applications. The possibility of modeling the transistors inthe 28 nm FD-SOI technology by means of the all inversion region long channelbulk transistor model used for the Schmitt trigger circuits, is studied. A cross-coupled nMOS architecture is used to build the VCO. The theoretical limit for theminimum supply voltage that enables oscillation is studied. The transistors wereoptimally sized to aim the minimum power consumption through a low-voltageapproach and the performance of the VCO was obtained through simulations. Los nodos sensores inalámbricos tienen fuertes requerimientos de bajo consumo demanera de operar con baterías pequeñas o algún mecanismo de cosecha de energía, o ambos. En muchos casos, la cosecha de energía térmica o electroquímica provee tensiones muy bajas del orden de 100 mV o incluso menos. Los sistemas de internet de las cosas incluyen un módulo de reloj que debe estar siempre encendido a efectos de contar el tiempo. Los osciladores a cristal son probadamente ́utiles como relojes de bajo consumo, y en este contexto la reducción de la tensión es una estrategia conveniente. Por lo tanto, presentamos osciladores a cristal de 32 kHz operando con sólo 60 mV de tensión de alimentación. Dos implementaciones, basadas en el circuito Schmitt trigger para dos cristales diferentes, se diseñan y caracterizan experimentalmente.Estos osciladores a cristal están basados en la aplicación del Schmitt trigger como amplificador. Se provee una guía para el diseño de este bloque para funcionar como el amplificador de un oscilador a cristal. Adicionalmente se propone un modelo dinámico del Schmitt trigger y los resultados del modelo son comparados con resultados de simulación. Los amplificadores son caracterizados experimentalmente, proveyendo una ganancia de 2.48 V/V con 60 mV de tensión de alimentación. Tal como se pretende en la etapa de diseño, para tensiones mayores a 100 mV aparece el fenómeno de histéresis y el Schmitt trigger comienza a operarcomo un comparador.Los Schmitt trigger para operar como amplificadores de los osciladores a cristal son diseñados en un proceso CMOS de 130 nm y ocupan un área de 45μm x 74μmy 78μm x 83μm, respectivamente. El consumo de potencia de sendos osciladores es2.26 nW y 15 nW y la estabilidad en temperatura obtenida es de 62 ppm (25-62°C)y 50 ppm (5-62°C), respectivamente. Se midieron la dependencia del consumo de corriente con respecto a la tensión de alimentación, la frequencia de oscilación, eltiempo de arranque y la amplitud de oscilación. La desviación de Allan es 30 ppben ambos osciladores.Por otra parte, un oscilador LC controlado por voltaje es diseñado en un proceso CMOS de silicio sobre aislante en deplexión total de 28 nm, para aplicaciones de radiofrecuencia. Se estudia la posibilidad de utilizar en este caso el mismo modelo utilizado para el diseño del Schmitt trigger. Dicho modelo es válido en todas las regiones de inversión y está desarrollado para transistores de tipo sustrato y de canal largo. La arquitectura de transistores nMOS entrelazados es la utilizada para este oscilador. Se estudia el límite teórico para la mínima tensión de alimentación. Los transistores son dimensionados de manera óptima para obtener el mínimo consumo de potencia posible, utilizando un enfoque de baja tensión y el desempeño del oscilador se obtuvo mediante simulaciones

On the design of ultra low voltage CMOS oscillators

Los nodos sensores inalámbricos tienen fuertes requerimientos de bajo consumo de manera de operar con baterías pequeñas o algún mecanismo de cosecha de energía, o ambos. En muchos casos, la cosecha de energía térmica o electroquímica provee tensiones muy bajas del orden de 100 mV o incluso menos. Los sistemas de internet de las cosas incluyen un módulo de reloj que debe estar siempre encendido a efectos de contar el tiempo. Los osciladores a cristal son probadamente útiles como relojes de bajo consumo, y en este contexto la reducción de la tensión es una estrategia conveniente. Por lo tanto, presentamos osciladores a cristal de 32 kHz operando con sólo 60 mV de tensión de alimentación. Dos implementaciones, basadas en el circuito Schmitt trigger para dos cristales diferentes, se diseñan y caracterizan experimentalmente. Estos osciladores a cristal están basados en la aplicación del Schmitt trigger como amplificador. Se provee una guía para el diseño de este bloque para funcionar como el amplificador de un oscilador a cristal. Adicionalmente se propone un modelo dinámico del Schmitt trigger y los resultados del modelo son comparados con resultados de simulación. Los amplificadores son caracterizados experimentalmente, proveyendo una ganancia de 2.48 V/V con 60 mV de tensión de alimentación. Tal como se pretende en la etapa de diseño, para tensiones mayores a 100 mV aparece el fenómeno de histéresis y el Schmitt trigger comienza a operar como un comparador. Los Schmitt trigger para operar como amplificadores de los osciladores a cristal son diseñados en un proceso CMOS de 130 nm y ocupan un área de 45 um x 74 um y 78 um x 83 um, respectivamente. El consumo de potencia de sendos osciladores es 2.26 nW y 15 nW y la estabilidad en temperatura obtenida es de 62 ppm (25-62°C) y 50 ppm (5-62°C), respectivamente. Se midieron la dependencia del consumo de corriente con respecto a la tensión de alimentación, la frequencia de oscilación, el tiempo de arranque y la amplitud de oscilación. La desviación de Allan es 30 ppb en ambos osciladores. Por otra parte, un oscilador LC controlado por voltaje es diseñado en un proceso CMOS de silicio sobre aislante en deplexión total de 28 nm, para aplicaciones de radiofrecuencia. Se estudia la posibilidad de utilizar en este caso el mismo modelo utilizado para el diseño del Schmitt trigger. Dicho modelo es válido en todas las regiones de inversión y está desarrollado para transistores de tipo sustrato y de canal largo. La arquitectura de transistores nMOS entrelazados es la utilizada para este oscilador. Se estudia el límite teórico para la mínima tensión de alimentación. Los transistores son dimensionados de manera óptima para obtener el mínimo consumo de potencia posible, utilizando un enfoque de baja tensión y el desempeño del oscilador se obtuvo mediante simulaciones.Agencia Nacional de Investigación e InnovaciónComisión Académica de Posgrado. Universidad de la RepúblicaComisión Sectorial de Investigación Científica. Universidad de la Repúblic

System-on-Package Low-Power Telemetry and Signal Conditioning unit for Biomedical Applications

Recent advancements in healthcare monitoring equipments and wireless communication technologies have led to the integration of specialized medical technology with the pervasive wireless networks. Intensive research has been focused on the development of medical wireless networks (MWN) for telemedicine and smart home care services. Wireless technology also shows potential promises in surgical applications. Unlike conventional surgery, an expert surgeon can perform the surgery from a remote location using robot manipulators and monitor the status of the real surgery through wireless communication link. To provide this service each surgical tool must be facilitated with smart electronics to accrue data and transmit the data successfully to the monitoring unit through wireless network. To avoid unwieldy wires between the smart surgical tool and monitoring units and to reap the benefit of excellent features of wireless technology, each smart surgical tool must incorporate a low-power wireless transmitter. Low-power transmitter with high efficiency is essential for short range wireless communication. Unlike conventional transmitters used for cellular communication, injection-locked transmitter shows greater promises in short range wireless communication. The core block of an injection-locked transmitter is an injection-locked oscillator. Therefore, this research work is directed towards the development of a low-voltage low-power injection-locked oscillator which will facilitate the development of a low-power injection-locked transmitter for MWN applications. Structure of oscillator and types of injection are two crucial design criteria for low-power injection-locked oscillator design. Compared to other injection structures, body-level injection offers low-voltage and low-power operation. Again, conventional NMOS/PMOS-only cross-coupled LC oscillator can work with low supply voltage but the power consumption is relatively high. To overcome this problem, a self-cascode LC oscillator structure has been used which provides both low-voltage and low-power operation. Body terminal coupling is used with this structure to achieve injection-locking. Simulation results show that the self-cascode structure consumes much less power compared to that of the conventional structure for the same output swing while exhibiting better phase noise performance. Usage of PMOS devices and body bias control not only reduces the flicker noise and power consumption but also eliminates the requirements of expensive fabrication process for body terminal access

RF CMOS Oscillators for Modern Wireless Applications

While mobile phones enjoy the largest production volume ever of any consumer electronics products, the demands they place on radio-frequency (RF) transceivers are particularly aggressive, especially on integration with digital processors, low area, low power consumption, while being robust against process-voltage-temperature variations. Since mobile terminals inherently operate on batteries, their power budget is severely constrained. To keep up with the ever increasing data-rate, an ever-decreasing power per bit is required to maintain the battery lifetime. The RF oscillator is the second most power-hungry block of a wireless radio (after power amplifiers). Consequently, any power reduction in an RF oscillator will greatly benefit the overall power efficiency of the cellular transceiver. Moreover, the RF oscillators' purity limits the transceiver performance. The oscillator's phase noise results in power leakage into adjacent channels in a transmit mode and reciprocal mixing in a receive mode. On the other hand, the multi-standard and multi-band transceivers that are now trending demand wide tuning range oscillators. However, broadening the oscillator’s tuning range is usually at the expense of die area (cost) or phase noise. The main goal of this book is to bring forth the exciting and innovative RF oscillator structures that demonstrate better phase noise performance, lower cost, and higher power efficiency than currently achievable. Technical topics discussed in RF CMOS Oscillators for Modern Wireless Applications include: Design and analysis of low phase-noise class-F oscillators Analyze a technique to reduce 1/f noise up-conversion in the oscillators Design and analysis of low power/low voltage oscillators Wide tuning range oscillators Reliability study of RF oscillators in nanoscale CMO

RF CMOS Oscillators for Modern Wireless Applications

While mobile phones enjoy the largest production volume ever of any consumer electronics products, the demands they place on radio-frequency (RF) transceivers are particularly aggressive, especially on integration with digital processors, low area, low power consumption, while being robust against process-voltage-temperature variations. Since mobile terminals inherently operate on batteries, their power budget is severely constrained. To keep up with the ever increasing data-rate, an ever-decreasing power per bit is required to maintain the battery lifetime. The RF oscillator is the second most power-hungry block of a wireless radio (after power amplifiers). Consequently, any power reduction in an RF oscillator will greatly benefit the overall power efficiency of the cellular transceiver. Moreover, the RF oscillators' purity limits the transceiver performance. The oscillator's phase noise results in power leakage into adjacent channels in a transmit mode and reciprocal mixing in a receive mode. On the other hand, the multi-standard and multi-band transceivers that are now trending demand wide tuning range oscillators. However, broadening the oscillator’s tuning range is usually at the expense of die area (cost) or phase noise. The main goal of this book is to bring forth the exciting and innovative RF oscillator structures that demonstrate better phase noise performance, lower cost, and higher power efficiency than currently achievable. Technical topics discussed in RF CMOS Oscillators for Modern Wireless Applications include: Design and analysis of low phase-noise class-F oscillators Analyze a technique to reduce 1/f noise up-conversion in the oscillators Design and analysis of low power/low voltage oscillators Wide tuning range oscillators Reliability study of RF oscillators in nanoscale CMO

Design of CMOS LC voltage controlled oscillators

This work presents the design and implementation of CMOS LC voltage controlled oscillators. On-chip planar spiral inductors and PMOS inversion mode varactors were utilized to implement the resonator. Two voltage controlled oscillators (VCOs) were realized as a part of this work, one designed to operate at 1.1 GHz while the second at 1.8 GHz. Both VCOs were implemented in a scalable digital CMOS process, with the former in a 1.5 micron CMOS process and the latter in a 0.5 micron technology. A simulation based methodology was adopted to arrive at a simple pi model used to model the metal and substrate related losses responsible for deteriorating the integrated inductor\u27s performance. Geometry based optimization techniques were utilized to arrive at an inductor geometry that ensures reasonable quality factor. In addition to the core VCO structure a host of test structures have been incorporated in order to carry out two-port network measurements in the future. Such measurements should enable one to gain a greater insight into the integrated inductor and varactor\u27s performance

An Energy-Efficient Reconfigurable Mobile Memory Interface for Computing Systems

The critical need for higher power efficiency and bandwidth transceiver design has significantly increased as mobile devices, such as smart phones, laptops, tablets, and ultra-portable personal digital assistants continue to be constructed using heterogeneous intellectual properties such as central processing units (CPUs), graphics processing units (GPUs), digital signal processors, dynamic random-access memories (DRAMs), sensors, and graphics/image processing units and to have enhanced graphic computing and video processing capabilities. However, the current mobile interface technologies which support CPU to memory communication (e.g. baseband-only signaling) have critical limitations, particularly super-linear energy consumption, limited bandwidth, and non-reconfigurable data access. As a consequence, there is a critical need to improve both energy efficiency and bandwidth for future mobile devices.;The primary goal of this study is to design an energy-efficient reconfigurable mobile memory interface for mobile computing systems in order to dramatically enhance the circuit and system bandwidth and power efficiency. The proposed energy efficient mobile memory interface which utilizes an advanced base-band (BB) signaling and a RF-band signaling is capable of simultaneous bi-directional communication and reconfigurable data access. It also increases power efficiency and bandwidth between mobile CPUs and memory subsystems on a single-ended shared transmission line. Moreover, due to multiple data communication on a single-ended shared transmission line, the number of transmission lines between mobile CPU and memories is considerably reduced, resulting in significant technological innovations, (e.g. more compact devices and low cost packaging to mobile communication interface) and establishing the principles and feasibility of technologies for future mobile system applications. The operation and performance of the proposed transceiver are analyzed and its circuit implementation is discussed in details. A chip prototype of the transceiver was implemented in a 65nm CMOS process technology. In the measurement, the transceiver exhibits higher aggregate data throughput and better energy efficiency compared to prior works

Data acquisition techniques based on frequency-encoding applied to capacitive MEMS microphones

Mención Internacional en el título de doctorThis thesis focuses on the development of capacitive sensor readout circuits and data converters based on frequency-encoding. This research has been motivated by the needs of consumer electronics industry, which constantly demands more compact readout circuit for MEMS microphones and other sensors. Nowadays, data acquisition is mainly based on encoding signals in voltage or current domains, which is becoming more challenging in modern deep submicron CMOS technologies. Frequency-encoding is an emerging signal processing technique based on encoding signals in the frequency domain. The key advantage of this approach is that systems can be implemented using mostly-digital circuitry, which benefits from CMOS technology scaling. Frequencyencoding can be used to build phase referenced integrators, which can replace classical integrators (such as switched-capacitor based integrators) in the implementation of efficient analog-to-digital converters and sensor interfaces. The core of the phase referenced integrators studied in this thesis consists of the combination of different oscillator topologies with counters and highly-digital circuitry. This work addresses two related problems: the development of capacitive MEMS sensor readout circuits based on frequency-encoding, and the design and implementation of compact oscillator-based data converters for audio applications. In the first problem, the target is the integration of the MEMS sensor into an oscillator circuit, making the oscillation frequency dependent on the sensor capacitance. This way, the sound can be digitized by measuring the oscillation frequency, using digital circuitry. However, a MEMS microphone is a complex structure on which several parasitic effects can influence the operation of the oscillator. This work presents a feasibility analysis of the integration of a MEMS microphone into different oscillator topologies. The conclusion of this study is that the parasitics of the MEMS limit the performance of the microphone, making it inefficient. In contrast, replacing conventional ADCs with frequency-encoding based ADCs has proven a very efficient solution, which motivates the next problem. In the second problem, the focus is on the development of high-order oscillator-based Sigma-Delta modulators. Firstly, the equivalence between classical integrators and phase referenced integrators has been studied, followed by an overview of state-of-art oscillator-based converters. Then, a procedure to replace classical integrators by phase referenced integrators is presented, including a design example of a second-order oscillator based Sigma-Delta modulator. Subsequently, the main circuit impairments that limit the performance of this kind of implementations, such as phase noise, jitter or metastability, are described. This thesis also presents a methodology to evaluate the impact of phase noise and distortion in oscillator-based systems. The proposed method is based on periodic steady-state analysis, which allows the rapid estimation of the system dynamic range without resorting to transient simulations. In addition, a novel technique to analyze the impact of clock jitter in Sigma-Delta modulators is described. Two integrated circuits have been implemented in 0.13 μm CMOS technology to demonstrate the feasibility of high-order oscillator-based Sigma-Delta modulators. Both chips have been designed to feature secondorder noise shaping using only oscillators and digital circuitry. The first testchip shows a malfunction in the digital circuitry due to the complexity of the multi-bit counters. The second chip, implemented using single-bit counters for simplicity, shows second-order noise shaping and reaches 103 dB-A of dynamic range in the audio bandwidth, occupying only 0.04 mm2.Esta tesis se centra en el desarrollo de conversores de datos e interfaces para sensores capacitivos basados en codificación en frecuencia. Esta investigación está motivada por las necesidades de la industria, que constantemente demanda reducir el tamaño de este tipo de circuitos. Hoy en día, la adquisición de datos está basada principalmente en la codificación de señales en tensión o en corriente. Sin embargo, la implementación de este tipo de soluciones en tecnologías CMOS nanométricas presenta varias dificultades. La codificación de frecuencia es una técnica emergente en el procesado de señales basada en codificar señales en el dominio de la frecuencia. La principal ventaja de esta alternativa es que los sistemas pueden implementarse usando circuitos mayoritariamente digitales, los cuales se benefician de los avances de la tecnología CMOS. La codificación en frecuencia puede emplearse para construir integradores referidos a la fase, que pueden reemplazar a los integradores clásicos (como los basados en capacidades conmutadas) en la implementación de conversores analógico-digital e interfaces de sensores. Los integradores referidos a la fase estudiados en esta tesis consisten en la combinación de diferentes topologías de osciladores con contadores y circuitos principalmente digitales. Este trabajo aborda dos cuestiones relacionadas: el desarrollo de circuitos de lectura para sensores MEMS capacitivos basados en codificación temporal, y el diseño e implementación de conversores de datos compactos para aplicaciones de audio basados en osciladores. En el primer caso, el objetivo es la integración de un sensor MEMS en un oscilador, haciendo que la frecuencia de oscilación depe capacidad del sensor. De esta forma, el sonido puede ser digitalizado midiendo la frecuencia de oscilación, lo cual puede realizarse usando circuitos en su mayor parte digitales. Sin embargo, un micrófono MEMS es una estructura compleja en la que múltiples efectos parasíticos pueden alterar el correcto funcionamiento del oscilador. Este trabajo presenta un análisis de la viabilidad de integrar un micrófono MEMS en diferentes topologías de oscilador. La conclusión de este estudio es que los parasíticos del MEMS limitan el rendimiento del micrófono, causando que esta solución no sea eficiente. En cambio, la implementación de conversores analógico-digitales basados en codificación en frecuencia ha demostrado ser una alternativa muy eficiente, lo cual motiva el estudio del siguiente problema. La segunda cuestión está centrada en el desarrollo de moduladores Sigma-Delta de alto orden basados en osciladores. En primer lugar se ha estudiado la equivalencia entre los integradores clásicos y los integradores referidos a la fase, seguido de una descripción de los conversores basados en osciladores publicados en los últimos años. A continuación se presenta un procedimiento para reemplazar integradores clásicos por integradores referidos a la fase, incluyendo un ejemplo de diseño de un modulador Sigma-Delta de segundo orden basado en osciladores. Posteriormente se describen los principales problemas que limitan el rendimiento de este tipo de sistemas, como el ruido de fase, el jitter o la metaestabilidad. Esta tesis también presenta un nuevo método para evaluar el impacto del ruido de fase y de la distorsión en sistemas basados en osciladores. El método propuesto está basado en simulaciones PSS, las cuales permiten la rápida estimación del rango dinámico del sistema sin necesidad de recurrir a simulaciones temporales. Además, este trabajo describe una nueva técnica para analizar el impacto del jitter de reloj en moduladores Sigma-Delta. En esta tesis se han implementado dos circuitos integrados en tecnología CMOS de 0.13 μm, con el fin de demostrar la viabilidad de los moduladores Sigma-Delta de alto orden basados en osciladores. Ambos chips han sido diseñados para producir conformación espectral de ruido de segundo orden, usando únicamente osciladores y circuitos mayoritariamente digitales. El primer chip ha mostrado un error en el funcionamiento de los circuitos digitales debido a la complejidad de las estructuras multi-bit utilizadas. El segundo chip, implementado usando contadores de un solo bit con el fin de simplificar el sistema, consigue conformación espectral de ruido de segundo orden y alcanza 103 dB-A de rango dinámico en el ancho de banda del audio, ocupando solo 0.04 mm2.Programa Oficial de Doctorado en Ingeniería Eléctrica, Electrónica y AutomáticaPresidente: Georges G.E. Gielen.- Secretario: José Manuel de la Rosa.- Vocal: Ana Rus