Wideband integrated circuits for optical communication systems

The exponential growth of internet traffic drives datacenters to constantly improvetheir capacity. Several research and industrial organizations are aiming towardsTbps Ethernet and beyond, which brings new challenges to the field of high-speedbroadband electronic circuit design. With datacenters rapidly becoming significantenergy consumers on the global scale, the energy efficiency of the optical interconnecttransceivers takes a primary role in the development of novel systems. Furthermore,wideband optical links are finding application inside very high throughput satellite(V/HTS) payloads used in the ever-expanding cloud of telecommunication satellites,enabled by the maturity of the existing fiber based optical links and the hightechnology readiness level of radiation hardened integrated circuit processes. Thereare several additional challenges unique in the design of a wideband optical system.The overall system noise must be optimized for the specific application, modulationscheme, PD and laser characteristics. Most state-of-the-art wideband circuits are builton high-end semiconductor SiGe and InP technologies. However, each technologydemands specific design decisions to be made in order to get low noise, high energyefficiency and adequate bandwidth. In order to overcome the frequency limitationsof the optoelectronic components, bandwidth enhancement and channel equalizationtechniques are used. In this work various blocks of optical communication systems aredesigned attempting to tackle some of the aforementioned challenges. Two TIA front-end topologies with 133 GHz bandwidth, a CB and a CE with shunt-shunt feedback,are designed and measured, utilizing a state-of-the-art 130 nm InP DHBT technology.A modular equalizer block built in 130 nm SiGe HBT technology is presented. Threeultra-wideband traveling wave amplifiers, a 4-cell, a single cell and a matrix single-stage, are designed in a 250 nm InP DHBT process to test the limits of distributedamplification. A differential VCSEL driver circuit is designed and integrated in a4x 28 Gbps transceiver system for intra-satellite optical communications based in arad-hard 130nm SiGe process

Silicon Photonic Subsystems for Inter-Chip Optical Networks

The continuous growth of electronic compute and memory nodes in terms of the number of I/O pins, bandwidth, and areal throughput poses major integration and packaging challenges associated with offloading multi-Tbit/s data rates within the few pJ/bit targets. While integrated photonics are already deployed in long and short distances such as inter and intra data centers communications, the promising characteristics of the silicon photonic platform set it as the future technology for optical interconnects in ultra short inter-chip distances. The high index contrast between the waveguide and the cladding together with strong thermo-optic and carrier effects in silicon allows developing a wide range of micro-scale and low power optical devices compatible with the CMOS fabrication processes. Furthermore, the availability of photonic foundries and new electrical and optical co-packaging techniques further pushes this platform for the next steps of commercial deployment. The work in this dissertation presents the current trends in high-performance memory and processor nodes and gives motivation for disaggregated and reconfigurable inter-chip network enabled with the silicon photonic layer. A dense WDM transceiver and broadband switch architectures are discussed to support a bi-directional network of ten hybrid-memory cubes (HMC) interconnected to ten processor nodes with an overall aggregated bandwidth of 9.6Tbit/s. Latency and energy consumption are key performance parameters in a processor to primary memory nodes connectivity. The transceiver design is based on energy-efficient micro-ring resonators, and the broadband switch is constructed with 2x2 Mach-Zehnder elements for nano-second reconfiguration. Each transceiver is based on hundreds of micro-rings to convert the native HMC electrical protocol to the optical domain and the switch is based on tens of hundreds of 2x2 elements to achieve non-blocking all-to-all connectivity. The next chapters focus on developing methods for controlling and monitoring such complex and highly integrated silicon photonic subsystems. The thermo-optic effect is characterized and we show experimentally that the phase of the optical carrier can be reliably controlled with pulse-width modulation (PWM) signal, ultimately relaxing the need for hundreds of digital to analog converters (DACs). We further show that doped waveguide heaters can be utilized as \textit{in-line} optical power monitors by measuring photo-conductance current, which is an alternative for the conventional tapping and integration of photo-diodes. The next part concerned with a common cascaded micro-ring resonator in a WDM transceiver design. We develop on an FPGA control algorithm that abstracts the physical layer and takes user-defined inputs to set the resonances to the desired wavelength in a unicast and multicast transmission modes. The associated sensitivities of these silicon ring resonators are presented and addressed with three closed-loop solutions. We first show a closed-loop operation based on tapping the error signal from the drop port of the micro-ring. The second solution presents a resonance wavelength locking with a single digital I/O for control and feedback signals. Lastly, we leverage the photo-conductance effect and demonstrate the locking procedure using only the doped heater for both control and feedback purposes. To achieve the inter-chip reconfigurability we discuss recent advances of high-port-count SiP broadband switches for reconfigurable inter-chip networks. To ensure optimal operation in terms of low insertion loss, low cross-talk and high signal integrity per routing path, hundreds of 2x2 Mach-Zehnder elements need to be biased precisely for the cross and bar states. We address this challenge with a tapless and a design agnostic calibration approach based on the photo-conductance effect. The automated algorithm returns a look-up table for all for each 2x2 element and the associated calibrated biases. Each routing scenario is then tested for insertion loss, crosstalk and bit-error rate of 25Gbit/s 4-level pulse amplitude modulation signals. The last part utilizes the Mach-Zehnder interferometers in WDM transceiver applications. We demonstrate a polarization insensitive four-channel WDM receiver with 40Gbit/s per channel and a transmitter design generating 8-level pulse amplitude modulation signals at 30Gbit/s

WDM/TDM PON bidirectional networks single-fiber/wavelength RSOA-based ONUs layer 1/2 optimization

This Thesis proposes the design and the optimization of a hybrid WDM/TDM PON at the L1 (PHY) and L2 (MAC) layers, in terms of minimum deployment cost and enhanced performance for Greenfield NGPON. The particular case of RSOA-based ONUs and ODN using a single-fibre/single-wavelength is deeply analysed. In this WDM/TDM PON relevant parameters are optimized. Special attention has been given at the main noise impairment in this type of networks: the Rayleigh Backscattering effect, which cannot be prevented. To understand its behaviour and mitigate its effects, a novel mathematical model for the Rayleigh Backscattering in burst mode transmission is presented for the first time, and it has been used to optimize the WDM/TDM RSOA based PON. Also, a cost-effective, simple design SCM WDM/TDM PON with rSOA-based ONU, was optimized and implemented. This prototype was successfully tested showing high performance, robustness, versatility and reliability. So, the system is able to give coverage up to 1280 users at 2.5 Gb/s / 1.25 Gb/s downstream/upstream, over 20 Km, and being compatible with the GPON ITU-T recommendation. This precedent has enabled the SARDANA network to extend the design, architecture and capabilities of a WDM/TDM PON for a long reach metro-access network (100 km). A proposal for an agile Transmission Convergence sub-layer is presented as another relevant contribution of this work. It is based on the optimization of the standards GPON and XG-PON (for compatibility), but applied to a long reach metro-access TDM/WDM PON rSOA-based network with higher client count. Finally, a proposal of physical implementation for the SARDANA layer 2 and possible configurations for SARDANA internetworking, with the metro network and core transport network, are presented

Coherent Optical OFDM Modem Employing Artificial Neural Networks for Dispersion and Nonlinearity Compensation in a Long-Haul Transmission System

In order to satisfy the ever increasing demand for the bandwidth requirement in broadband services the optical orthogonal frequency division multiplexing (OOFDM) scheme is being considered as a promising technique for future high-capacity optical networks. The aim of this thesis is to investigate, theoretically, the feasibility of implementing the coherent optical OFDM (CO-OOFDM) technique in long haul transmission networks. For CO-OOFDM and Fast-OFDM systems a set of modulation formats dependent analogue to digital converter (ADC) clipping ratio and the quantization bit have been identified, moreover, CO-OOFDM is more resilient to the chromatic dispersion (CD) when compared to the bandwidth efficient Fast-OFDM scheme. For CO-OOFDM systems numerical simulations are undertaken to investigate the effect of the number of sub-carriers, the cyclic prefix (CP), and ADC associated parameters such as the sampling speed, the clipping ratio, and the quantisation bit on the system performance over single mode fibre (SMF) links for data rates up to 80 Gb/s. The use of a large number of sub-carriers is more effective in combating the fibre CD compared to employing a long CP. Moreover, in the presence of fibre non-linearities identifying the optimum number of sub-carriers is a crucial factor in determining the modem performance. For a range of signal data rates up to 40 Gb/s, a set of data rate and transmission distance-dependent optimum ADC parameters are identified in this work. These parameters give rise to a negligible clipping and quantisation noise, moreover, ADC sampling speed can increase the dispersion tolerance while transmitting over SMF links. In addition, simulation results show that the use of adaptive modulation schemes improves the spectrum usage efficiency, thus resulting in higher tolerance to the CD when compared to the case where identical modulation formats are adopted across all sub-carriers. For a given transmission distance utilizing an artificial neural networks (ANN) equalizer improves the system bit error rate (BER) performance by a factor of 50% and 70%, respectively when considering SMF firstly CD and secondly nonlinear effects with CD. Moreover, for a fixed BER of 10-3 utilizing ANN increases the transmission distance by 1.87 times and 2 times, respectively while considering SMF CD and nonlinear effects. The proposed ANN equalizer performs more efficiently in combating SMF non-linearities than the previously published Kerr nonlinearity electrical compensation technique by a factor of 7

Améliorations des transmissions VLC (Visible Light Communication) sous contrainte d'éclairage : études théoriques et expérimentations

Abstract : Indoor visible light communication (VLC) networks based on light-emitting diodes (LEDs) currently enjoy growing interest thanks in part to their robustness against interference, wide license-free available bandwidth, low cost, good energy efficiency and compatibility with existing lighting infrastructure. In this thesis, we investigate spectral-efficient modulation techniques for the physical layer of VLC to increase throughput while considering the quality of illumination as well as implementation costs. Numerical and experimental studies are performed employing pulse amplitude modulation (PAM) and carrierless amplitude and phase (CAP) modulation under illumination constraints and for high modulation orders. Furthermore, the impact of LED nonlinearity is investigated and a postdistortion technique is evaluated to compensate these nonlinear effects. Within this framework, transmission rates in the order of a few hundred Mb/s are achieved using a test bench made of low-cost components. In addition, an imaging multiple input multiple-output (MIMO) system is developed and the impact on performance of imaging lens misalignment is theoretically and numerically assessed. Finally, a polynomial matrix decomposition technique based on the classical LU factorization method is studied and applied for the first time to MIMO VLC systems in large space indoor environments.Les réseaux de communication en lumière visible (VLC) s’appuyant sur l’utilisation de diodes électroluminescentes (LED) bénéficient actuellement d’un intérêt grandissant, en partie grâce à leur robustesse face aux interférences électromagnétiques, leur large bande disponible non-régulée, leur faible coût, leur bonne efficacité énergétique, ainsi que leur compatibilité avec les infrastructures d’éclairage déjà existantes. Dans cette thèse, nous étudions des techniques de modulation à haute efficacité spectrale pour la couche physique des VLC pour augmenter les débits tout en considérant la qualité de l’éclairage ainsi que les coûts d’implémentation. Des études numériques et expérimentales sont réalisées sur la modulation d’impulsion d’amplitude (PAM) et sur la modulation d’amplitude et de phase sans porteuse (CAP) sous des contraintes d’éclairage et pour des grands ordres de modulation. De plus, l’impact des non-linéarités de la LED est étudié et une technique de post-distorsion est évaluée pour corriger ces effets non-linéaires. Dans ce cadre, des débits de plusieurs centaines de Mb/s sont atteints en utilisant un banc de test réalisé à partir de composants à bas coûts. Par ailleurs, un système multi-entrées multi-sorties (MIMO) imageant est également développé et l’impact du désaxage de l’imageur sur les performances est étudié. Finalement, une technique de décomposition polynomiale basée sur la méthode de factorisation classique LU est étudiée et appliquée aux systèmes MIMO VLC dans des grands espaces intérieurs

Modular Optical Wireless Elements

Optical wireless has gained attention in recent years as an e cient and secure way to provide broadband connectivity to mobile platforms, isolated communities, and crowded public events. Companies like NASA, Google, Facebook, and others have demonstrated its potential. However, current optical wireless technology remains mostly heavy, bulky, and expensive, making it impractical for many scenarios and inaccessible to most students/researchers. This work presents the concept of Modular Optical Wireless Elements (MOWE), a novel system composed of multiple electrically interconnected optical modules (i.e., elements) forming a at or curved terminal that is inexpensive, lightweight, and easy-to-assemble. The technology enables cost-eff ective access to wide eld-of-view optical communication for last-mile broadband connectivity. Smart modules provide recon gurability, as well as local and central processing capabilities. The modules enable innovative short- and medium-range applications for free-space optics (FSO) in indoor communication and navigation, MIMO, and optical sensing, among others. This dissertation introduces the MOWE concept and provides in-depth information about modeling, analysis, hardware, and rmware, along with proof-of-concept examples and demonstrations. The notions of software-de ned optics and cognitive optics are introduced and analyzed in a MOWE context. Several experiments and case studies covering a wide spectrum of applications-from intelligent power control to passive beam steering-are presented in detail. This dissertation also discusses the future of MOWE technology and suggests possible improvements for high performance systems

Hybrid NRZ/Multi-Tone Signaling for High-Speed Low-Power Wireline Transceivers

Over the past few decades, incessant growth of Internet networking traffic and High-Performance Computing (HPC) has led to a tremendous demand for data bandwidth. Digital communication technologies combined with advanced integrated circuit scaling trends have enabled the semiconductor and microelectronic industry to dramatically scale the bandwidth of high-loss interfaces such as Ethernet, backplane, and Digital Subscriber Line (DSL). The key to achieving higher bandwidth is to employ equalization technique to compensate the channel impairments such as Inter-Symbol Interference (ISI), crosstalk, and environmental noise. Therefore, todayâs advanced input/outputs (I/Os) has been equipped with sophisticated equalization techniques to push beyond the uncompensated bandwidth of the system. To this end, process scaling has continually increased the data processing capability and improved the I/O performance over the last 15 years. However, since the channel bandwidth has not scaled with the same pace, the required signal processing and equalization circuitry becomes more and more complicated. Thereby, the energy efficiency improvements are largely offset by the energy needed to compensate channel impairments. In this design paradigm, re-thinking about the design strategies in order to not only satisfy the bandwidth performance, but also to improve power-performance becomes an important necessity. It is well known in communication theory that coding and signaling schemes have the potential to provide superior performance over band-limited channels. However, the choice of the optimum data communication algorithm should be considered by accounting for the circuit level power-performance trade-offs. In this thesis we have investigated the application of new algorithm and signaling schemes in wireline communications, especially for communication between microprocessors, memories, and peripherals. A new hybrid NRZ/Multi-Tone (NRZ/MT) signaling method has been developed during the course of this research. The system-level and circuit-level analysis, design, and implementation of the proposed signaling method has been performed in the frame of this work, and the silicon measurement results have proved the efficiency and the robustness of the proposed signaling methodology for wireline interfaces. In the first part of this work, a 7.5 Gb/s hybrid NRZ/MT transceiver (TRX) for multi-drop bus (MDB) memory interfaces is designed and fabricated in 40 nm CMOS technology. Reducing the complexity of the equalization circuitry on the receiver (RX) side, the proposed architecture achieves 1 pJ/bit link efficiency for a MDB channel bearing 45 dB loss at 2.5 GHz. The measurement results of the first prototype confirm that NRZ/MT serial data TRX can offer an energy-efficient solution for MDB memory interfaces. Motivated by the satisfying results of the first prototype, in the second phase of this research we have exploited the properties of multi-tone signaling, especially orthogonality among different sub-bands, to reduce the effect of crosstalk in high-dense wireline interconnects. A four-channel transceiver has been implemented in a standard CMOS 40 nm technology in order to demonstrate the performance of NRZ/MT signaling in presence of high channel loss and strong crosstalk noise. The proposed system achieves 1 pJ/bit power efficiency, while communicating over a MDB memory channel at 36 Gb/s aggregate data rate

Transmissores-recetores de baixa complexidade para redes óticas

Traditional coherent (COH) transceivers allow encoding of information in both quadratures and the two orthogonal polarizations of the electric field. Nevertheless, such transceivers used today are based on the intradyne scheme, which requires two 90o optical hybrids and four pairs of balanced photodetectors for dual-polarization transmission systems, making its overall cost unattractive for short-reach applications. Therefore, SSB methods with DD reception, commonly referred to as self-coherent (SCOH) transceivers, can be employed as a cost-effective alternative to the traditional COH transceivers. Nevertheless, the performance of SSB systems is severely degraded. This work provides a novel SCOH transceiver architecture with improved performance for short-reach applications. In particular, the development of phase reconstruction digital signal processing (DSP) techniques, the development of other DSP subsystems that relax the hardware requirement, and their performance optimization are the main highlights of this research. The fundamental principle of the proposed transceiver is based on the reception of the signal that satisfies the minimum phase condition upon DD. To reconstruct the missing phase information imposed by DD, a novel DCValue method exploring the SSB and the DC-Value properties of the minimum phase signal is developed in this Ph.D. study. The DC-Value method facilitates the phase reconstruction process at the Nyquist sampling rate and requires a low intensity pilot signal. Also, the experimental validation of the DC-Value method was successfully carried out for short-reach optical networks. Additionally, an extensive study was performed on the DC-Value method to optimize the system performance. In the optimization process, it was found that the estimation of the CCF is an important parameter to exploit all advantages of the DC-Value method. A novel CCF estimation technique was proposed. Further, the performance of the DC-Value method is optimized employing the rate-adaptive probabilistic constellation shaping.Os sistemas de transcetores coerentes tradicionais permitem a codificação de informação em ambas quadraturas e em duas polarizações ortogonais do campo elétrico. Contudo, estes transcetores utilizados atualmente são baseados num esquema intradino, que requer dois híbridos óticos de 90o e quatro pares de foto detetores para sistemas de transmissão com polarização dupla, fazendo com que o custo destes sistemas seja pouco atrativo para aplicações de curto alcance. Por isso, métodos de banda lateral única com deteção direta, também referidos como transcetores coerentes simplificados, podem ser implementados como uma alternativa de baixo custo aos sistemas coerentes tradicionais. Contudo, o desempenho de sistemas de banda lateral única tradicionais é gravemente degradado pelo batimento sinal-sinal. Nesta tese foi desenvolvida uma nova arquitetura de transcetor coerente simplificada com um melhor desempenho para aplicações de curto alcance. Em particular, o desenvolvimento de técnicas de processamento digital de sinal para a reconstrução de fase, bem como de outros subsistemas de processamento digital de sinal que minimizem os requerimentos de hardware e a sua otimização de desempenho são o foco principal desta tese. O princípio fundamental do transcetor proposto é baseado na receção de um sinal que satisfaz a condição mínima de fase na deteção direta. Para reconstruir a informação de fase em falta causada pela deteção direta, um novo método de valor DC que explora sinais de banda lateral única e as propriedades DC da condição de fase mínima é desenvolvido nesta tese. O método de valor DC facilita a reconstrução da fase à frequência de amostragem de Nyquist e requer um sinal piloto de baixa intensidade. Além disso, a validação experimental do método de valor DC foi executada com sucesso em ligações óticas de curto alcance. Adicionalmente, foi realizado um estudo intensivo do método de valor DC para otimizar o desempenho do sistema. Neste processo de otimização, verificou-se que o fator de contribuição da portadora é um parâmetro importante para explorar todas as vantagens do método de valor DC. Neste contexto, é proposto um novo método para a sua estimativa. Por último, o desempenho do método de valor DC é otimizado recorrendo a mapeamento probabilístico de constelação com taxa adaptativa.Programa Doutoral em Engenharia Eletrotécnic

Analysis and Design of High Speed Serial Interfaces for Automotive Applications

The demand for an enriched end-user experience and increased performance in next generation electronic applications is never ending, and it is a common trend for a wide spectrum of applications owing to different markets, like computing, mobile communication and automotive. For this reason High Speed Serial Interface have become widespread components for nowadays electronics with a constant demand for power reduction and data rate increase. In the frame of gigabit serial systems, the work discussed in this thesis develops in two directions: on one hand, the aim is to support the continuous data rate increase with the development of novel link modeling approaches that will be employed for system level evaluation and as support in the design and characterization phases. On the other hand, the design considerations and challenges in the implementation of the transmitter, one of the most delicate blocks for the signal integrity performance of the link, are central. The first part of the activity regarding link performance predictions lead to the development of an enhanced statistical simulation approach, capable to account for the transmitter waveform shape in the ISI analysis, a characteristic that is missed by the available state-ofthe- art simulation approaches. The proposed approach has been extensively tested by comparison with traditional simulation approaches (Spice-like simulators) and validated against experimental characterization of a test system, with satisfactory results. The second part of the activity consists in the design of a high speed transmitter in a deeply scaled CMOS technology, spanning from the concept of the circuit, its implementation and characterization. Targets of the design are to achieve a data rate of 5 Gb/s with a minimum voltage swing of 800 mV, thus doubling the data rate of the current transmitter implementation, and reduce the power dissipation adopting a voltage mode architecture. The experimental characterization of the fabricated lot draws a twofold picture, with some of the performance figures showing a very good qualitative and quantitative agreement with pre-silicon simulations, and others revealing a poor performance level, especially for the eye diagram. Investigation of the root causes by the analysis of the physical silicon design, of the bonding scheme of the prototypes and of the pre-silicon simulations is reported. Guidelines for the redesign of the circuit are also given.Nel panorama delle applicazioni elettroniche il miglioramento delle performance di un prodotto da una generazione alla successiva ha lo scopo di offrire all\u2019utilizzatore finale nuove funzioni e migliorare quelle esistenti. Negli ultimi anni grazie al costante avanzamento della tecnologia integrata, si \ue8 assistito ad un enorme sviluppo della capacit\ue0 computazionale dei dispositivi in tutti i segmenti di mercato, quali ad esempio l\u2019information technology, la comunicazione mobile e l\u2019automotive. La conseguente necessit\ue0 di mettere in comunicazione dispostivi diversi all\u2019interno della stessa applicazione e di traferire grosse quantit\ue0 di dati ha provocato una capillare diffusione delle interfacce seriali ad alta velocit\ue0, o High Speed Serial Interfaces (HSSIs). La necessit\ue0 di ridurre il consumo di potenza e aumentare il bit rate per questo tipo di applicazioni \ue8 diventata dunque un ambito di ricerca di estremo interesse. Il lavoro discusso in questa tesi si colloca nell\u2019ambito della trasmissione di dati seriali a bit rate superiori ad 1Gb/s e si sviluppa in due direzioni: da un lato, a sostegno del continuo aumento del bit rate nelle nuove generazioni di interfacce, \ue8 stato affrontato lo sviluppo di nuovi approcci di modellazione del sistema, che possano essere impiegati nella valutazione delle prestazioni dell\u2019interfaccia e a supporto delle fasi di progettazione e di caratterizzazione. Dall\u2019altro lato, si \ue8 focalizzata l\u2019attenzione sulle sfide e sulle problematiche inerenti il progetto di uno dei blocchi pi\uf9 delicati per le prestazioni del sistema, il trasmettitore. La prima parte della tesi ha come oggetto lo sviluppo di un approccio di simulazione statistico innovativo, in grado di includere nell\u2019analisi degli effetti dell\u2019interferenza di intersimbolo anche la forma d\u2019onda prodotta all\u2019uscita del trasmettitore, una caratteristica che non \ue8 presente in altri approcci di simulazione proposti in letteratura. La tecnica proposta \ue8 ampiamente testata mediante il confronto con approcci di simulazione tradizionali (di tipo Spice) e mediante il confronto con la caratterizzazione sperimentale di un sistema di test, con risultati pienamente soddisfacenti. La seconda parte dell\u2019attivit\ue0 riguarda il progetto di un trasmettitore integrato high speed in tecnologia CMOS a 40nm e si estende dallo studio di fattibilit\ue0 del circuito fino alla sua realizzazione e caratterizzazione. Gli obiettivi riguardano il raggiungimento di un bit rate pari a 5 Gb/s, raddoppiando cos\uec il bit rate dell\u2019attuale implementazione, e di una tensione differenziale di uscita minima di 800mV (picco-picco) riducendo allo stesso tempo la potenza dissipata mediante l\u2019adozione di una architettura Voltage Mode. I risultati sperimentali ottenuti dal primo lotto fabbricato non delineano un quadro univoco: alcune performance mostrano un ottimo accordo qualitativo e quantitativo con le simulazioni pre-fabbricazione, mentre prestazioni non soddisfacenti sono state ottenute in particolare per il diagramma ad occhio. Grazie all\u2019analisi del layout del prototipo, del bonding tra silicio e package e delle simulazioni pre-fabbricazione \ue8 stato possibile risalire ai fattori responsabili del degrado delle prestazioni rispetto alla previsioni pre-fabbricazione, permettendo inoltre di delineare le linee guida da seguire nella futura progettazione di un nuovo prototipo

Modelling and performance analysis of multigigabit serial interconnects using real number based analog verification methods

The increasing importance of multigigabit transceiver circuits in modern chip design calls for new methods of analyzing and integrating these challenging building blocks. This work presents a design and analysis framework basend on the SystemVerilog real number modeling ansatz. It further extends the simulation possibilities thus obtained by introducing additional higher level numeric modelling and evaluation methods to support multigigabit statistical link budgeting procedures based on the Peak Distortion Algorithm