LOW-JITTER AND LOW-SPUR RING-OSCILLATOR-BASED PHASE-LOCKED LOOPS

Department of Electrical EngineeringIn recent years, ring-oscillator based clock generators have drawn a lot of attention due to the merits of high area efficiency, potentially wide tuning range, and multi-phase generation. However, the key challenge is how to suppress the poor jitter of ring oscillators. There have been many efforts to develop a ring-oscillator-based clock generator targeting very low-jitter performance. However, it remains difficult for conventional architectures to achieve both low RMS jitter and low levels of reference spurs concurrently while having a high multiplication factor. In this dissertation, a time-domain analysis is presented that provides an intuitive understanding of RMS jitter calculation of the clock generators from their phase-error correction mechanisms. Based on this analysis, we propose new designs of a ring-oscillator-based PLL that addresses the challenges of prior-art ring-based architectures. This dissertation introduces a ring-oscillator-based PLL with the proposed fast phase-error correction (FPEC) technique, which emulates the phase-realignment mechanism of an injection-locked clock multiplier (ILCM). With the FPEC technique, the phase error of the voltage-controlled oscillator (VCO) is quickly removed, achieving ultra-low jitter. In addition, in the transfer function of the proposed architecture, an intrinsic integrator is involved since it is naturally based on a PLL topology. The proposed PLL can thus have low levels of reference spurs while maintaining high stability even for a large multiplication factor. Furthermore, it presents another design of a digital PLL embodying the FPEC technique (or FPEC DPLL). To overcome the problem of a conventional TDC, a low-power optimally-spaced (OS) TDC capable of effectively minimizing the quantization error is presented. In the proposed FPEC DPLL, background digital controllers continuously calibrate the decision thresholds and the gain of the error correction by the loop to be optimal, thus dramatically reducing the quantization error. Since the proposed architecture is implemented in a digital fashion, the variables defining the characteristics of the loop can be easily estimated and calibrated by digital calibrators. As a result, the performances of an ultra-low jitter and the figure-of-merit can be achieved.clos

차량용 CIS Interface 를 위한 All-Digital Phase-Locked Loop 의 설계 및 분석

학위논문 (석사) -- 서울대학교 대학원 : 공과대학 전기·정보공학부, 2021. 2. 정덕균.This thesis presents design techniques for All-Digital Phase-Locked Loop (ADPLL) assisting the automotive CMOS image sensor (CIS) interface. To target Gear 3 of the automotive physical system, the proposed AD-PLL has a wide operation range, low RMS jitter, and high PVT tolerance characteristics. Detailed analysis of the loop dynamics and the noise analysis of AD-PLL are done by using Matlab and Verilog behavioral modeling simulation before an actual design. Based on that analysis, the optimal DLF gain configurations are yielded, and also, accurate output responses and performance are predictable. The design techniques to reduce the output RMS jitter are discussed thoroughly and utilized for actual implementation. The proposed AD-PLL is fabricated in the 40 nm CMOS process and occupies an effective area of 0.026 mm2. The PLL output clock pulses exhibit an RMS jitter of 827 fs at 2 GHz. The power dissipation is 5.8 mW at 2 GHz, where the overall supply voltage domain is 0.9 V excluding the buffer which is 1.1 V domain.본 논문에서는 자동차 CMOS 이미지 센서 (CIS) 인터페이스를 지원하 는 AD-PLL 을 제안한다. Automotive Physical 시스템의 Gear 3 를 지원하기 위해 제안된 AD-PLL 은 1.5 GHz 에서 3 GHz 의 동작 주파수를 가지며, 낮 은 RMS Jitter 및 PVT 변화에 대한 높은 둔감성을 갖는다. 설계에 앞서서 Matlab 및 Verilog Behavioral Simulation 을 통해 Loop system 의 역학에 대한 자세한 분석 및 AD-PLL 의 Noise 분석을 수행하였고, 이 분석을 기반으로 최적의 DLF gain 과 정확한 출력 응답 및 성능을 예측 할 수 있었다. 또한, 출력의 Phase Noise 와 RMS Jitter 를 줄이기 위한 설계 기법을 자세히 다루고 있으며 이를 실제 구현에 활용했다. 제안된 회로는 40 nm CMOS 공정으로 제작되었으며 Decoupling Cap 을 제외하고 0.026 mm2 의 유효 면적을 차지한다. 측정된 출력 Clock 신호의 RMS Jitter 값은 2 GHz 에서 827 fs 이며, 총 5.8 mW의 Power 를 소비한다. 이 때, 전체적인 공급 전압은 0.9 V 이며, Buffer 의 Power 만이 1.1 V 를 사용하 였다.ABSTRACT I CONTENTS II LIST OF FIGURES IV LIST OF TABLES VII CHAPTER 1 INTRODUCTION 1 1.1 MOTIVATION 1 1.2 THESIS ORGANIZATION 3 CHAPTER 2 BACKGROUND ON ALL-DIGITAL PLL 4 2.1 OVERVIEW 4 2.2 BUILDING BLOCKS OF AD-PLL 7 2.2.1 TIME-TO-DIGITAL CONVERTER 7 2.2.2 DIGITALLY-CONTROLLED OSCILLATOR 10 2.2.3 DIGITAL LOOP FILTER 13 2.2.4 DELTA-SIGMA MODULATOR 16 2.3 PHASE NOISE ANALYSIS OF AD-PLL 20 2.3.1 BASIC ASSUMPTION OF LINEAR ANALYSIS 20 2.3.2 NOISE SOURCES OF AD-PLL 21 2.3.3 EFFECTS OF LOOP DELAY ON AD-PLL 24 2.3.4 PHASE NOISE ANALYSIS OF PROPOSED AD-PLL 26 CHAPTER 3 DESIGN OF ALL-DIGITAL PLL 28 3.1 DESIGN CONSIDERATION 28 3.2 OVERALL ARCHITECTURE 30 3.3 CIRCUIT IMPLEMENTATION 32 3.3.1 PFD-TDC 32 3.3.2 DCO 37 3.3.3 DIGITAL BLOCK 43 3.3.4 LEVEL SHIFTING BUFFER AND DIVIDER 45 CHAPTER 4 MEASUREMENT AND SIMULATION RESULTS 52 4.1 DIE PHOTOMICROGRAPH 52 4.2 MEASUREMENT SETUP 54 4.3 TRANSIENT ANALYSIS 57 4.4 PHASE NOISE AND SPUR PERFORMANCE 59 4.4.1 FREE-RUNNING DCO 59 4.4.2 PLL PERFORMANCE 61 4.5 PERFORMANCE SUMMARY 65 CHAPTER 5 CONCLUSION 67 BIBLIOGRAPHY 68 초 록 72Maste

캘리브레이션이 필요없는 위상고정 루프의 설계

학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2017. 2. 김재하.A PVT-insensitive-bandwidth PLL and a chirp frequency synthesizer PLL are proposed using a constant-relative-gain digitally-controlled oscillator (DCO), a constant-gain time-to-digital converter (TDC), and a simple digital loop filter (DLF) without an explicit calibration or additional circuit components. A digital LC-PLL that realizes a PVT-insensitive loop bandwidth (BW) by using the constant-relative-gain LC-DCO and constant-gain TDC is proposed. In other words, based on ratiometric circuit designs, the LC-DCO can make a fixed percent change to its frequency for a unit change in its digital input and the TDC can maintain a fixed range and resolution measured in reference unit intervals (UIs) across PVT variations. With such LC-DCO and TDC, the proposed PLL can realize a bandwidth which is a constant fraction of the reference frequency even with a simple proportional-integral digital loop filter without any explicit calibration loops. The prototype digital LC-PLL fabricated in a 28-nm CMOS demonstrates a frequency range of 8.38~9.34 GHz and 652-fs,rms integrated jitter from 10-kHz to 1-GHz at 8.84-GHz while dissipating 15.2-mW and occupying 0.24-mm^2. Also, the PLL across three different die samples and supply voltage ranging from 1.0 to 1.2V demonstrates a nearly constant BW at 822-kHz with the variation of ±4.25-% only. A chirp frequency synthesizer PLL (FS-PLL) that is capable of precise triangular frequency modulation using type-III digital LC-PLL architecture for X-band FMCW imaging radar is proposed. By employing a phase-modulating two-point modulation (TPM), constant-gain TDC, and a simple second-order DLF with polarity-alternating frequency ramp estimator, the PLL achieves a gain self-tracking TPM realizing a frequency chirp with fast chirp slope (=chirp BW/chirp period) without increasing frequency errors around the turn-around points, degrading the effective resolution achievable. A prototype chirp FS-PLL fabricated in a 65nm CMOS demonstrates that the PLL can generate a precise triangular chirp profile centered at 8.9-GHz with 940-MHz bandwidth and 28.8-us period with only 1.9-MHz,rms frequency error including the turn-around points and 14.8-mW power dissipation. The achieved 32.63-MHz/us chirp slope is higher than that of FMCW FS-PLLs previously reported by 2.6x.CHAPTER 1 INTRODUCTION 1 1.1 MOTIVATION 1 1.2 THESIS ORGANIZATION 5 CHAPTER 2 CONVENTIONAL PHASE-LOCKED LOOP 7 2.1 CHARGE-PUMP PLL 7 2.1.1 OPERATING PRINCIPLE 7 2.1.2 LOOP DYNAMICS 9 2.2 DIGITAL PLL 10 2.2.1 OPERATING PRINCIPLE 11 2.2.2 LOOP DYNAMICS 12 CHAPTER 3 VARIATIONS ON PHASE-LOCKED LOOP 14 3.1 OSCILLATOR GAIN VARIATION 14 3.1.1 RING VOLTAGE-CONTROLLED OSCILLATOR 15 3.1.2 LC VOLTAGE-CONTROLLED OSCILLATOR 17 3.1.3 LC DIGITALLY-CONTROLLED OSCILLATOR 19 3.2 PHASE DETECTOR GAIN VARIATION 20 3.2.1 LINEAR PHASE DETECTOR 20 3.2.2 LINEAR TIME-TO-DIGITAL CONVERTER 21 CHAPTER 4 PROPOSED DCO AND TDC FOR CALIBRATION-FREE PLL 23 4.1 DIGTALLY-CONTROLLED OSCILLATOR (DCO) 25 4.1.1 OVERVIEW 24 4.1.2 CONSTANT-RELATIVE-GAIN DCO 26 4.2 TIME-TO-DIGITAL CONVERTER (TDC) 28 4.2.1 OVERVIEW 28 4.2.2 CONSTANT-GAIN TDC 30 CHAPTER 5 PVT-INSENSITIVE-BANDWIDTH PLL 35 5.1 OVERVIEW 36 5.2 PRIOR WORKS 37 5.3 PROPOSED PVT-INSENSITIVE-BANDWIDTH PLL 39 5.4 CIRCUIT IMPLEMENTATION 41 5.4.1 CAPACITOR-TUNED LC-DCO 41 5.4.2 TRANSFORMER-TUNED LC-DCO 45 5.4.3 OVERSAMPLING-BASED CONSTANT-GAIN TDC 49 5.4.4 PHASE DIGITAL-TO-ANALOG CONVERTER 52 5.4.5 DIGITAL LOOP FILTER 54 5.4.6 FREQUENCY DIVIDER 55 5.4.7 BANG-BANG PHASE-FREQUENCY DETECTOR 56 5.5 CELL-BASED DESIGN FLOW 57 5.6 MEASUREMENT RESULTS 58 CHAPTER 6 CHIRP FREQUENCY SYNTHESIZER PLL 66 6.1 OVERVIEW 67 6.2 PRIOR WORKS 71 6.3 PROPOSED CHIRP FREQUENCY SYNTHESIZER PLL 75 6.4 CIRCUIT IMPLEMENTATION 83 6.4.1 SECOND-ORDER DIGITAL LOOP FILTER 83 6.4.2 PHASE MODULATOR 84 6.4.3 CONSTANT-GAIN TDC 85 6.4.4 VRACTOR-BASED LC-DCO 87 6.4.5 OVERALL CLOCK CHAIN 90 6.5 MEASUREMENT RESULTS 91 6.6 SIGNAL-TO-NOISE RATIO OF RADAR 98 CHAPTER 7 CONCLUSION 100 BIBLIOGRAPHY 102 초록 109Docto

Self-Calibrated, Low-Jitter and Low-Reference-Spur Injection-Locked Clock Multipliers

Department of Electrical EngineeringThis dissertation focuses primarily on the design of calibrators for the injection-locked clock multiplier (ILCM). ILCMs have advantage to achieve an excellent jitter performance at low cost, in terms of area and power consumption. The wide loop bandwidth (BW) of the injection technique could reject the noise of voltage-controlled oscillator (VCO), making it thus suitable for the rejection of poor noise of a ring-VCO and a high frequency LC-VCO. However, it is difficult to use without calibrators because of its sensitiveness in process-voltage-temperature (PVT) variations. In Chapter 2, conventional frequency calibrators are introduced and discussed. This dissertation introduces two types of calibrators for low-power high-frequency LC-VCO-based ILFMs in Chapter 3 and Chapter 4 and high-performance ring-VCO-based ILCM in Chapter 5. First, Chapter 3 presents a low power and compact area LC-tank-based frequency multiplier. In the proposed architecture, the input signals have a pulsed waveform that involves many high-order harmonics. Using an LC-tank that amplifies only the target harmonic component, while suppressing others, the output signal at the target frequency can be obtained. Since the core current flows for a very short duration, due to the pulsed input signals, the average power consumption can be dramatically reduced. Effective removal of spurious tones due to the damping of the signal is achieved using a limiting amplifier. In this work, a prototype frequency tripler using the proposed architecture was designed in a 65 nm CMOS process. The power consumption was 950 ??W, and the active area was 0.08 mm2. At a 3.12 GHz frequency, the phase noise degradation with respect to the theoretical bound was less than 0.5 dB. Second, Chapter 4 presents an ultra-low-phase-noise ILFM for millimeter wave (mm-wave) fifth-generation (5G) transceivers. Using an ultra-low-power frequency-tracking loop (FTL), the proposed ILFM is able to correct the frequency drifts of the quadrature voltage-controlled oscillator of the ILFM in a real-time fashion. Since the FTL is monitoring the averages of phase deviations rather than detecting or sampling the instantaneous values, it requires only 600??W to continue to calibrate the ILFM that generates an mm-wave signal with an output frequency from 27 to 30 GHz. The proposed ILFM was fabricated in a 65-nm CMOS process. The 10-MHz phase noise of the 29.25-GHz output signal was ???129.7 dBc/Hz, and its variations across temperatures and supply voltages were less than 2 dB. The integrated phase noise from 1 kHz to 100 MHz and the rms jitter were???39.1 dBc and 86 fs, respectively. Third, Chapter 5 presents a low-jitter, low-reference-spur ring voltage-controlled oscillator (ring VCO)-based ILCM. Since the proposed triple-point frequency/phase/slope calibrator (TP-FPSC) can accurately remove the three root causes of the frequency errors of ILCMs (i.e., frequency drift, phase offset, and slope modulation), the ILCM of this work is able to achieve a low-level reference spur. In addition, the calibrating loop for the frequency drift of the TP-FPSC offers an additional suppression to the in-band phase noise of the output signal. This capability of the TP-FPSC and the naturally wide bandwidth of the injection-locking mechanism allows the ILCM to achieve a very low RMS jitter. The ILCM was fabricated in a 65-nm CMOS technology. The measured reference spur and RMS jitter were ???72 dBc and 140 fs, respectively, both of which are the best among the state-of-the-art ILCMs. The active silicon area was 0.055 mm2, and the power consumption was 11.0 mW.clos

Design of energy efficient high speed I/O interfaces

Energy efficiency has become a key performance metric for wireline high speed I/O interfaces. Consequently, design of low power I/O interfaces has garnered large interest that has mostly been focused on active power reduction techniques at peak data rate. In practice, most systems exhibit a wide range of data transfer patterns. As a result, low energy per bit operation at peak data rate does not necessarily translate to overall low energy operation. Therefore, I/O interfaces that can scale their power consumption with data rate requirement are desirable. Rapid on-off I/O interfaces have a potential to scale power with data rate requirements without severely affecting either latency or the throughput of the I/O interface. In this work, we explore circuit techniques for designing rapid on-off high speed wireline I/O interfaces and digital fractional-N PLLs. A burst-mode transmitter suitable for rapid on-off I/O interfaces is presented that achieves 6 ns turn-on time by utilizing a fast frequency settling ring oscillator in digital multiplying delay-locked loop and a rapid on-off biasing scheme for current mode output driver. Fabricated in 90 nm CMOS process, the prototype achieves 2.29 mW/Gb/s energy efficiency at peak data rate of 8 Gb/s. A 125X (8 Gb/s to 64 Mb/s) change in effective data rate results in 67X (18.29 mW to 0.27 mW) change in transmitter power consumption corresponding to only 2X (2.29 mW/Gb/s to 4.24 mW/Gb/s) degradation in energy efficiency for 32-byte long data bursts. We also present an analytical bit error rate (BER) computation technique for this transmitter under rapid on-off operation, which uses MDLL settling measurement data in conjunction with always-on transmitter measurements. This technique indicates that the BER bathtub width for 10^(−12) BER is 0.65 UI and 0.72 UI during rapid on-off operation and always-on operation, respectively. Next, a pulse response estimation-based technique is proposed enabling burst-mode operation for baud-rate sampling receivers that operate over high loss channels. Such receivers typically employ discrete time equalization to combat inter-symbol interference. Implementation details are provided for a receiver chip, fabricated in 65nm CMOS technology, that demonstrates efficacy of the proposed technique. A low complexity pulse response estimation technique is also presented for low power receivers that do not employ discrete time equalizers. We also present techniques for implementation of highly digital fractional-N PLL employing a phase interpolator based fractional divider to improve the quantization noise shaping properties of a 1-bit ∆Σ frequency-to-digital converter. Fabricated in 65nm CMOS process, the prototype calibration-free fractional-N Type-II PLL employs the proposed frequency-to-digital converter in place of a high resolution time-to-digital converter and achieves 848 fs rms integrated jitter (1 kHz-30 MHz) and -101 dBc/Hz in-band phase noise while generating 5.054 GHz output from 31.25 MHz input

Design of High-Speed SerDes Transceiver for Chip-to-Chip Communications in CMOS Process

With the continuous increase of on-chip computation capacities and exponential growth of data-intensive applications, the high-speed data transmission through serial links has become the backbone for modern communication systems. To satisfy the massive data-exchanging requirement, the data rate of such serial links has been updated from several Gb/s to tens of Gb/s. Currently, the commercial standards such as Ethernet 400GbE, InfiniBand high data rate (HDR), and common electrical interface (CEI)-56G has been developing towards 40+ Gb/s. As the core component within these links, the transceiver chipset plays a fundamental role in balancing the operation speed, power consumption, area occupation, and operation range. Meanwhile, the CMOS process has become the dominant technology in modern transceiver chip fabrications due to its large-scale digital integration capability and aggressive pricing advantage. This research aims to explore advanced techniques that are capable of exploiting the maximum operation speed of the CMOS process, and hence provides potential solutions for 40+ Gb/s CMOS transceiver designs. The major contributions are summarized as follows. A low jitter ring-oscillator-based injection-locked clock multiplier (RILCM) with a hybrid frequency tracking loop that consists of a traditional phase-locked loop (PLL), a timing-adjusted loop, and a loop selection state-machine is implemented in 65-nm C-MOS process. In the ring voltage-controlled oscillator, a full-swing pseudo-differential delay cell is proposed to lower the device noise to phase noise conversion. To obtain high operation speed and high detection accuracy, a compact timing-adjusted phase detector tightly combined with a well-matched charge pump is designed. Meanwhile, a lock-loss detection and lock recovery is devised to endow the RILCM with a similar lock-acquisition ability as conventional PLL, thus excluding the initial frequency set- I up aid and preventing the potential lock-loss risk. The experimental results show that the figure-of-merit of the designed RILCM reaches -247.3 dB, which is better than previous RILCMs and even comparable to the large-area LC-ILCMs. The transmitter (TX) and receiver (RX) chips are separately designed and fab- ricated in 65-nm CMOS process. The transmitter chip employs a quarter-rate multi-multiplexer (MUX)-based 4-tap feed-forward equalizer (FFE) to pre-distort the output. To increase the maximum operating speed, a bandwidth-enhanced 4:1 MUX with the capability of eliminating charge-sharing effect is proposed. To produce the quarter-rate parallel data streams with appropriate delays, a compact latch array associated with an interleaved-retiming technique is designed. The receiver chip employs a two-stage continuous-time linear equalizer (CTLE) as the analog front-end and integrates an improved clock data recovery to extract the sampling clocks and retime the incoming data. To automatically balance the jitter tracking and jitter suppression, passive low-pass filters with adaptively-adjusted bandwidth are introduced into the data-sampling path. To optimize the linearity of the phase interpolation, a time-averaging-based compensating phase interpolator is proposed. For equalization, a combined TX-FFE and RX-CTLE is applied to compensate for the channel loss, where a low-cost edge-data correlation-based sign zero-forcing adaptation algorithm is proposed to automatically adjust the TX-FFE’s tap weights. Measurement results show that the fabricated transmitter/receiver chipset can deliver 40 Gb/s random data at a bit error rate of 16 dB loss at the half-baud frequency, while consuming a total power of 370 mW

Ultra Low-Power Frequency Synthesizers for Duty Cycled IoT radios

Internet of Things (IoT), which is one of the main talking points in the electronics industry today, consists of a number of highly miniaturized sensors and actuators which sense the physical environment around us and communicate that information to a central information hub for further processing. This agglomeration of miniaturized sensors helps the system to be deployed in previously impossible arenas such as healthcare (Body Area Networks - BAN), industrial automation, real-time monitoring environmental parameters and so on; thereby greatly improving the quality of life. Since the IoT devices are usually untethered, their energy sources are limited (typically battery powered or energy scavenging) and hence have to consume very low power. Today's IoT systems employ radios that use communication protocols like Bluetooth Smart; which means that they communicate at data rates of a few hundred kb/s to a few Mb/s while consuming around a few mW of power. Even though the power dissipation of these radios have been decreasing steadily over the years, they seem to have reached a lower limit in the recent times. Hence, there is a need to explore other avenues to further reduce this dissipation so as to further improve the energy autonomy of the IoT node. Duty cycling has emerged as a promising alternative in this sense since it involves radios transmitting very short bursts of data at high rates and being asleep the rest of the time. In addition, high data rates proffer the added advantage of reducing network congestion which has become a major problem in IoT owing to the increase in the number of sensor nodes as well as the volume of data they send. But, as the average power (energy) dissipated decreases due to duty cycling, the energy overhead associated with the start-up phase of the radio becomes comparable with the former. Therefore, in order to take full advantage of duty cycling, the radio should be capable of being turned ON/OFF almost instantaneously. Furthermore, the radio of the future should also be able to support easy frequency hopping to improve the system efficiency from an interference point of view. In other words, in addition to high data rate capability, the next generation radios must also be highly agile and have a low energy overhead. All these factors viz. data rate, agility and overhead are mainly dependent on the radio's frequency synthesizer and therefore emphasis needs to be laid on developing new synthesizer architectures which are also amenable to technology scaling. This thesis deals with the evolution of one such all-digital frequency synthesizer; with each step dealing with one of the aforementioned issues. In order to reduce the energy overhead of the synthesizer, FBAR resonators (which are a class of MEMS resonators) are used as the frequency reference instead of a traditional quartz crystal. The FBAR resonators aid the design of fast-startup oscillators as opposed to the long latency associated with the start-up of the crystal oscillator. In addition, the frequency stability of the FBAR lends itself to open-loop architecture which can support very high data rates. Another advantage of the open-loop architecture is the frequency agility which aids easy channel switching for multi-hop architectures, as demonstrated in this thesis

Low Power Circuit Design in Sustainable Self Powered Systems for IoT Applications

The Internet-of-Things (IoT) network is being vigorously pushed forward from many fronts in diverse research communities. Many problems are still there to be solved, and challenges are found among its many levels of abstraction. In this thesis we give an overview of recent developments in circuit design for ultra-low power transceivers and energy harvesting management units for the IoT. The first part of the dissertation conducts a study of energy harvesting interfaces and optimizing power extraction, followed by power management for energy storage and supply regulation. we give an overview of the recent developments in circuit design for ultra-low power management units, focusing mainly in the architectures and techniques required for energy harvesting from multiple heterogeneous sources. Three projects are presented in this area to reach a solution that provides reliable continuous operation for IoT sensor nodes in the presence of one or more natural energy sources to harvest from. The second part focuses on wireless transmission, To reduce the power consumption and boost the Tx energy efficiency, a novel delay cell exploiting current reuse is used in a ring-oscillator employed as the local oscillator generator scheme. In combination with an edge-combiner power amplifier, the Tx showed a measured energy efficiency of 0.2 nJ=bit and a normalized energy efficiency of 3.1 nJ=bit:mW when operating at output power levels up to -10 dBm and data rates of 3 Mbps

A 320-fs RMS Jitter and-75-dBc Reference-Spur Ring-DCO-Based Digital PLL Using an Optimal-Threshold TDC

This paper presents a ring-type, digitally controlled oscillator (DCO)-based integer-N digital phase-locked loop (DPLL) that can achieve low jitter and low reference spur concurrently. In order to minimize the quantization error, while consuming a small amount of power, this work presents an optimal-threshold (OT) time-to-digital converter (TDC). The thresholds of the OT TPC and the phase-correction gain of the loop are corrected continuously in the background. The PLL was fabricated in a 65-nm CMOS process and its measured rms jitter integrated from 1 kHz to 100 MHz and the reference spur of a 2.4-GHz frequency were 320 fs and -75 dBc, respectively. Through measurement, they were verified to be maintained robustly over temperature and supply variations. The active area was 0.055 mm(2), and the power consumption was 6.0 mW