A 0.3V 1kb Sub-Threshold SRAM for Ultra-Low-Power Application in 90nm CMOS

[[notice]]缺頁數[[conferencetype]]國際[[conferencedate]]20120715~20120718[[booktype]]電子版[[iscallforpapers]]Y[[conferencelocation]]Sapporo, Japa

A 300mV 10MHz 4kb 10T Subthreshold SRAM for Ultralow-Power Application

[[notice]]缺頁數[[conferencetype]]國際[[conferencedate]]20121104~20121107[[booktype]]電子版[[iscallforpapers]]Y[[conferencelocation]]New Taipei City, Taiwa

Design of Low Power SRAM Cell Using 10Transistors

The primary aim of electronics is to design low power devices due to the frequent usage of powered widget. The memory cell operation containing low voltage consumption hasbecome a major interest in designing of memory cells due to its applications in very low energy computing.Due to specification modifications in scaled methodologies, the only critical method isstable operation of SRAM for the success of low voltage design of SRAM. Along with the power and voltage consumption, due to unwanted switching actions of transistors, the access time of the SRAM is also considered as a complex parameter and it is used for different blocks like, designed SRAM cell, access transistors, pre-charge circuit, decoders and sense amplifiers.The conventional 6T SRAM are unable toachievethe less delay and sub threshold operation. The proposed design is designed by using the sleep transistor circuits. The sleep transistor circuits are turned to be ON in active state and in OFF state during passive state.A supply voltage of 1.8V is used which enough for low power applications in energy computing. The designed SRAM cell has conducting pMOS circuit, which can also reduces the total power dissipation. The designed 10T SRAM cell reduces 40.56% of total power and 17.86% of total delay compared with the conventional 6T SRAM cell.The structured SRAM cell is reproduced by utilizing Cadence device of 180nm innovation

Design of Low Power SRAM Cell Using 10Transistors

The primary aim of electronics is to design low power devices due to the frequent usage of powered widget. The memory cell operation containing low voltage consumption hasbecome a major interest in designing of memory cells due to its applications in very low energy computing.Due to specification modifications in scaled methodologies, the only critical method isstable operation of SRAM for the success of low voltage design of SRAM. Along with the power and voltage consumption, due to unwanted switching actions of transistors, the access time of the SRAM is also considered as a complex parameter and it is used for different blocks like, designed SRAM cell, access transistors, pre-charge circuit, decoders and sense amplifiers.The conventional 6T SRAM are unable toachievethe less delay and sub threshold operation. The proposed design is designed by using the sleep transistor circuits. The sleep transistor circuits are turned to be ON in active state and in OFF state during passive state.A supply voltage of 1.8V is used which enough for low power applications in energy computing. The designed SRAM cell has conducting pMOS circuit, which can also reduces the total power dissipation. The designed 10T SRAM cell reduces 40.56% of total power and 17.86% of total delay compared with the conventional 6T SRAM cell.The structured SRAM cell is reproduced by utilizing Cadence device of 180nm innovation

Single event upset mitigation in low power SRAM design

Logic compatible gain cell (GC)-embedded DRAM (eDRAM) arrays are considered an alternative to SRAM due to their small size, nonratioed operation, low static leakage, and two-port functionality. However, traditional GC-eDRAM implementations require boosted control signals in order to write full voltage levels to the cell to reduce the refresh rate and shorten access times. These boosted levels require either an extra power supply or on-chip charge pumps, as well as nontrivial level shifting and toleration of high voltage levels. In this brief, we present a novel, logic compatible, 3T GC-eDRAM bitcell that operates with a single-supply voltage and provides superior write capability to the conventional GC structures. The proposed circuit is demonstrated with a 2-kb memory macro that was designed and fabricated in a mature 0.18-μm CMOS process, targeted at low-power, energy-efficient applications. The test array is powered with a single supply of 900 mV, showing a 0.8-ms worst case retention time, a 1.3-ns write-access time, and a 2.4-pW/bit retention power. The proposed topology provides a bitcell area reduction of 43%, as compared with a redrawn 6-transistor SRAM in the same technology, and an overall macro area reduction of 67% including peripherals

Ultra-low Power FinFET SRAM Cell with improved stability suitable for low power applications

In this paper, a new 11T SRAM cell using FinFET technology has been proposed, the basic component of the cell is the 6T SRAM cell with 4 NMOS access transistors to improve the stability and also makes it a dual port memory cell. The proposed cell uses a header scheme in which one extra PMOS transistor is used which is biased at different voltages to improve the read and write stability thus, helps in reducing the leakage power and active power. The cell shows improvement in RSNM (Read Static Noise Margin) with LP8T by 2.39x at sub-threshold voltage 2.68x with D6T SRAM cell, 5.5x with TG8T. The WSNM (Write Static Noise Margin) and HM (Hold Margin) of the SRAM cell at 0.9V is 306mV and 384mV. At sub-threshold operation also it shows improvement. The Leakage power reduced by 0.125x with LP8T, 0.022x with D6T SRAM cell, TG8T and SE8T. Also, impact of process variation on cell stability is discussed

Ultra-Low-Power Embedded SRAM Design for Battery- Operated and Energy-Harvested IoT Applications

Internet of Things (IoT) devices such as wearable health monitors, augmented reality goggles, home automation, smart appliances, etc. are a trending topic of research. Various IoT products are thriving in the current electronics market. The IoT application needs such as portability, form factor, weight, etc. dictate the features of such devices. Small, portable, and lightweight IoT devices limit the usage of the primary energy source to a smaller rechargeable or non-rechargeable battery. As battery life and replacement time are critical issues in battery-operated or partially energy-harvested IoT devices, ultra-low-power (ULP) system on chips (SoC) are becoming a widespread solution of chip makers’ choice. Such ULP SoC requires both logic and the embedded static random access memory (SRAM) in the processor to operate at very low supply voltages. With technology scaling for bulk and FinFET devices, logic has demonstrated to operate at low minimum operating voltages (VMIN). However, due to process and temperature variation, SRAMs have higher VMIN in scaled processes that become a huge problem in designing ULP SoC cores. This chapter discusses the latest published circuits and architecture techniques to minimize the SRAM VMIN for scaled bulk and FinFET technologies and improve battery life for ULP IoT applications