Communication Subsystems for Emerging Wireless Technologies

The paper describes a multi-disciplinary design of modern communication systems. The design starts with the analysis of a system in order to define requirements on its individual components. The design exploits proper models of communication channels to adapt the systems to expected transmission conditions. Input filtering of signals both in the frequency domain and in the spatial domain is ensured by a properly designed antenna. Further signal processing (amplification and further filtering) is done by electronics circuits. Finally, signal processing techniques are applied to yield information about current properties of frequency spectrum and to distribute the transmission over free subcarrier channels

A wide dynamic range high-q high-frequency bandpass filter with an automatic quality factor tuning scheme

An 80 MHz bandpass filter with a tunable quality factor of 16∼44 using an improved transconductor circuit is presented. A noise optimized biquad structure for high-Q, high- frequency bandpass filter is proposed. The quality factor of the filter is tuned using a new quality factor locked loop algorithm. It was shown that a second-order quality factor locked loop is necessary and sufficient to tune the quality factor of a bandpass filter with zero steady state error. The accuracy, mismatch, and sensitivty analysis of the new tuning scheme was performed and analyzed. Based on the proposed noise optimized filter structure and new quality factor tuning scheme, a biquad filter was designed and fabricated in 0.25 μm BiCMOS process. The measured results show that the biquad filter achieves a SNR of 45 dB at IMD of 40 dB. The P-1dB compression point and IIP3 of the filter are -10 dBm and -2.68 dBm, respectively. The proposed biquad filter and quality factor tuning scheme consumes 58mW and 13 mW of power at 3.3 V supply.Ph.D.Committee Chair: Allen Phillip; Committee Member: Hasler Paul; Committee Member: Keezer David; Committee Member: Kenny James; Committee Member: Pan Ronghu

Realization of Integrable Low- Voltage Companding Filters for Portable System Applications

Undoubtedly, today’s integrated electronic systems owe their remarkable performance primarily to the rapid advancements of digital technology since 1970s. The various important advantages of digital circuits are: its abstraction from the physical details of the actual circuit implementation, its comparative insensitiveness to variations in the manufacturing process, and the operating conditions besides allowing functional complexity that would not be possible using analog technology. As a result, digital circuits usually offer a more robust behaviour than their analog counterparts, though often with area, power and speed drawbacks. Due to these and other benefits, analog functionality has increasingly been replaced by digital implementations. In spite of the advantages discussed above, analog components are far from obsolete and continue to be key components of modern electronic systems. There is a definite trend toward persistent and ubiquitous use of analog electronic circuits in day-to-day life. Portable electronic gadgets, wireless communications and the widespread application of RF tags are just a few examples of contemporary developments. While all of these electronic systems are based on digital circuitry, they heavily rely on analog components as interfaces to the real world. In fact, many modern designs combine powerful digital systems and complementary analog components on a single chip for cost and reliability reasons. Unfortunately, the design of such systems-on-chip (SOC) suffers from the vastly different design styles of analog and digital components. While mature synthesis tools are readily available for digital designs, there is hardly any such support for analog designers apart from wellestablished PSPICE-like circuit simulators. Consequently, though the analog part usually occupies only a small fraction of the entire die area of an SOC, but its design often constitutes a major bottleneck within the entire development process. Integrated continuous-time active filters are the class of continuous-time or analog circuits which are used in various applications like channel selection in radios, anti-aliasing before sampling, and hearing aids etc. One of the figures of merit of a filter is the dynamic range; this is the ratio of the largest to the smallest signal that can be applied at the input of the filter while maintaining certain specified performance. The dynamic range required in the filter varies with the application and is decided by the variation in strength of the desired signal as well as that of unwanted signals that are to be rejected by the filter. It is well known that the power dissipation and the capacitor area of an integrated active filter increases in proportion to its dynamic range. This situation is incompatible with the needs of integrated systems, especially battery operated ones. In addition to this fundamental dependence of power dissipation on dynamic range, the design of integrated active filters is further complicated by the reduction of supply voltage of integrated circuits imposed by the scaling down of technologies to attain twin objective of higher speed and lower power consumption in digital circuits. The reduction in power consumption with decreasing supply voltage does not apply to analog circuits. In fact, considerable innovation is required with a reduced supply voltage even to avoid increasing power consumption for a given signal to noise ratio (S/N). These aspects pose a great hurdle to the active filter designer. A technique which has attracted the attention of circuit designers as a possible route to filters with higher dynamic range per unit power consumption is “companding”. Companding (compression-expansion) filters are a very promising subclass of continuous-time analog filters, where the input (linear) signal is initially compressed before it will be handled by the core (non-linear) system. In order to preserve the linear operation of the whole system, the non-linear signal produced by the core system is converted back to a linear output signal by employing an appropriate output stage. The required compression and expansion operations are performed by employing bipolar transistors in active region or MOS transistors in weak inversion; the systems thus derived are known as logarithmic-domain (logdomain) systems. In case MOS transistors operated in saturation region are employed, the derived structures are known as Square-root domain systems. Finally, the third class of companding filters can also be obtained by employing bipolar transistors in active region or MOS transistors in weak inversion; the derived systems are known as Sinh-domain systems. During the last several years, a significant research effort has been already carried out in the area of companding circuits. This is due to the fact that their main advantages are the capability for operation in low-voltage environment and large dynamic range originated from their companding nature, electronic tunability of the frequency characteristics, absence of resistors and the potential for operations in varied frequency regions.Thus, it is obvious that companding filters can be employed for implementing high-performance analog signal processing in diverse frequency ranges. For example, companding filters could be used for realizing subsystems in: xDSL modems, disk drive read channels, biomedical electronics, Bluetooth/ZigBee applications, phaselocked loops, FM stereo demodulator, touch-tone telephone tone decoder and crossover network used in a three-way high-fidelity loudspeaker etc. A number of design methods for companding filters and their building blocks have been introduced in the literature. Most of the proposed filter structures operate either above 1.5V or under symmetrical (1.5V) power supplies. According to data that provides information about the near future of semiconductor technology, International Technology Roadmap for Semiconductors (ITRS), in 2013, the supply voltage of digital circuits in 32 nm technology will be 0.5 V. Therefore, the trend for the implementation of analog integrated circuits is the usage of low-voltage building blocks that use a single 0.5-1.5V power supply. Therefore, the present investigation was primarily concerned with the study and design of low voltage and low power Companding filters. The work includes the study about: the building blocks required in implementing low voltage and low power Companding filters; the techniques used to realize low voltage and low power Companding filters and their various areas of application. Various novel low voltage and low power Companding filter designs have been developed and studied for their characteristics to be applied in a particular portable area of application. The developed designs include the N-th order universal Companding filter designs, which have been reported first time in the open literature. Further, an endeavor has been made to design Companding filters with orthogonal tuning of performance parameters so that the designs can be simultaneously used for various features. The salient features of each of the developed circuit are described. Electronic tunability is one of the major features of all of the designs. Use of grounded capacitors and resistorless designs in all the cases makes the designs suitable for IC technology. All the designs operate in a low-voltage and low-power environment essential for portable system applications. Unless specified otherwise, all the investigations on these designs are based on the PSPICE simulations using model parameters of the NR100N bipolar transistors and BSIM 0.35μm/TSMC 0.25μm /TSMC 0.18μm CMOS process MOS transistors. The performance of each circuit has been validated by comparing the characteristics obtained using simulation with the results present in the open literature. The proposed designs could not be realized in silicon due to non-availability of foundry facility at the place of study. An effort has already been started to realize some of the designs in silicon and check their applicability in practical circuits. At the basic level, one of the proposed Companding filter designs was implemented using the commercially available transistor array ICs (LM3046N) and was found to verify the theoretical predictions obtained from the simulation results

Design of PVT Tolerant Inverter Based Circuits for Low Supply Voltages

University of Minnesota Ph.D. dissertation. June 2015. Major: Electrical Engineering. Advisor: Ramesh Harjani. 1 computer file (PDF); xiv, 187 pages.Rapid advances in the field of integrated circuit design has been advantageous from the point of view of cost and miniaturization. Although technology scaling is advantageous to digital circuits in terms of increased speed and lower power, analog circuits strongly suffer from this trend. This is becoming a crucial bottle neck in the realization of a system on chip in scaled technology merging high-density digital parts, with high performance analog interfaces. This is because scaled technologies reduce the output impedance (gain) and supply voltage which limits the dynamic range (output swing). One way to mitigate the power supply restrictions is to move to current mode circuit circuit design rather than voltage mode designs. This thesis focuses on designing Process Voltage and Temperature (PVT) tolerant base band circuits at lower supply voltages and in lower technologies. Inverter amplifiers are known to have better transconductance efficiency, better noise and linearity performance. But inverters are prone to PVT variations and has poor CMRR and PSRR. To circumvent the problem, we have proposed various biasing schemes for inverter like semi constant current biasing, constant current biasing and constant gm biasing. Each biasing technique has its own advantages, like semi constant current biasing allows to select different PMOS and NMOS current. This feature allows for higher inherent inverter linearity. Similarly constant current and constant gm biasing allows for reduced PVT sensitivity. The inverter based OTA achieves a measured THD of -90.6 dB, SNR of 78.7 dB, CMRR 97dB, PSRR 61 dB wile operating from a nominal power of 0.9V and at output swing of 0.9V{pp,diff} in TSMC 40nm general purpose process. Further the measured third harmonic distortion varies approximately by 11.5dB with 120C variation in temperature and 9dB with a 18% variation in supply voltage. The linearity can be increased by increasing the loop gain and bandwidth in a negative feedback circuit or by increasing the over drive voltage in open loop architectures. However both these techniques increases the noise contribution of the circuit. There exist a trade off between noise and linearity in analog circuits. To circumvent this problem, we have introduced nonlinear cancellation techniques and noise filtering techniques. An analog-to-digital converter (ADC) driver which is capable of amplifying the continuous time signal with a gain of 8 and sample onto the input capacitor(1pF) of 1 10 bit successive approximation register (SAR) ADC is designed in TSMC 65nm general purpose process. This exploits the non linearity cancellation in current mirror and also allows for higher bandwidth operation by decoupling closed loop gain from the negative feedback loop. The noise from the out of band is filtered before sampling leading to low noise operation. The measured design operates at 100MS/s and has an OIP_3 of 40dBm at the nyquist rate, noise power spectral density of 17nV/sqrt{Hz} and inter modulation distortion of 65dB. The intermodulation distortion variation across 10 chips is 6dB and 4dB across a temperature variation of 120C. Non linearity cancellation is exploited in designing two filters, an anti alias filter and a continuously tunable channel select filter. Traditional active RC filters are based on cascade of integrators. These create multiple low impedance nodes in the circuit which results in a higher noise. We propose a real low pass filter based filter architecture rather than traditional integrator based approach. Further the entire filtering operation takes place in current domain to circumvent the power supply limitations. This also facilitates the use of tunable non linear metal oxide semiconductor capacitor (MOSCAP) as filter capacitors. We introduce techniques of self compensation to use the filter resistor and capacitor as compensation capacitor for lower power. The anti alias filter designed for 50MHz bandwidth is fabricated in IBM 65nm process achieves an IIP3 of 33dBm, while consuming 1.56mW from 1.2 V supply. The channel select filter is tunable from 34MHz to 314MHz and is fabricated in TSMC 65nm general purpose process. This filter achieves an OIP3 of 25.24 dBm at the maximum frequency while drawing 4.2mA from 1.1V supply. The measured intermodulation distortion varies by 5dB across 120C variation in temperature and 6.5dB across a 200mV variation in power supply. Further this filter presents a high impedance node at the input and a low impedance node at the output easing system integration. SAR ADCs are becoming popular at lower technologies as they are based on device switching rather than amplifying circuits. But recent SAR ADCs that have good energy efficiency have had relatively large input capacitance increasing the driver power. We present a 2X time interleaved (TI) SAR ADC which has the lowest input capacitance of 133fF in literature. The sampling capacitor is separated from the capacitive digital to analog converter (DAC) array by performing the input and DAC reference subtraction in the current domain rather than as done traditionally in charge domain. The proposed ADC is fabricated in TSMC's 65nm general purpose process and occupies an area of 0.0338 mm^2. The measured ADC spurious free dynamic range (SFDR) is 57dB and the measured effective number of bits (ENOB) at nyquist rate is 7.55 bit while using 1.55mW power from 1 V supply. A sub 1V reference circuit is proposed, that exploits the complementary to absolute temperature (CTAT) and proportional to absolute temperature (PTAT) voltages in the beta multiplier circuit to attain a stable voltage with temperature and power supply. A one-time calibration is integrated in the architecture to get a good performance over process. Chopper stabilization is employed to reduce the flicker noise of the reference circuit. The prototype was simulated in TSMC 65nm process and we obtain the nominal output of 236mW, while consuming 0.7mW from power supply. Simulations show a temperature coefficient of 18 ppmC from -40 to 100C and with a power supply ranging from 0.8 to 2V

Low Voltage Low Power Analogue Circuits Design

Disertační práce je zaměřena na výzkum nejběžnějších metod, které se využívají při návrhu analogových obvodů s využití nízkonapěťových (LV) a nízkopříkonových (LP) struktur. Tyto LV LP obvody mohou být vytvořeny díky vyspělým technologiím nebo také využitím pokročilých technik návrhu. Disertační práce se zabývá právě pokročilými technikami návrhu, především pak nekonvenčními. Mezi tyto techniky patří využití prvků s řízeným substrátem (bulk-driven - BD), s plovoucím hradlem (floating-gate - FG), s kvazi plovoucím hradlem (quasi-floating-gate - QFG), s řízeným substrátem s plovoucím hradlem (bulk-driven floating-gate - BD-FG) a s řízeným substrátem s kvazi plovoucím hradlem (quasi-floating-gate - BD-QFG). Práce je také orientována na možné způsoby implementace známých a moderních aktivních prvků pracujících v napěťovém, proudovém nebo mix-módu. Mezi tyto prvky lze začlenit zesilovače typu OTA (operational transconductance amplifier), CCII (second generation current conveyor), FB-CCII (fully-differential second generation current conveyor), FB-DDA (fully-balanced differential difference amplifier), VDTA (voltage differencing transconductance amplifier), CC-CDBA (current-controlled current differencing buffered amplifier) a CFOA (current feedback operational amplifier). Za účelem potvrzení funkčnosti a chování výše zmíněných struktur a prvků byly vytvořeny příklady aplikací, které simulují usměrňovací a induktanční vlastnosti diody, dále pak filtry dolní propusti, pásmové propusti a také univerzální filtry. Všechny aktivní prvky a příklady aplikací byly ověřeny pomocí PSpice simulací s využitím parametrů technologie 0,18 m TSMC CMOS. Pro ilustraci přesného a účinného chování struktur je v disertační práci zahrnuto velké množství simulačních výsledků.The dissertation thesis is aiming at examining the most common methods adopted by analog circuits' designers in order to achieve low voltage (LV) low power (LP) configurations. The capability of LV LP operation could be achieved either by developed technologies or by design techniques. The thesis is concentrating upon design techniques, especially the non–conventional ones which are bulk–driven (BD), floating–gate (FG), quasi–floating–gate (QFG), bulk–driven floating–gate (BD–FG) and bulk–driven quasi–floating–gate (BD–QFG) techniques. The thesis also looks at ways of implementing structures of well–known and modern active elements operating in voltage–, current–, and mixed–mode such as operational transconductance amplifier (OTA), second generation current conveyor (CCII), fully–differential second generation current conveyor (FB–CCII), fully–balanced differential difference amplifier (FB–DDA), voltage differencing transconductance amplifier (VDTA), current–controlled current differencing buffered amplifier (CC–CDBA) and current feedback operational amplifier (CFOA). In order to confirm the functionality and behavior of these configurations and elements, they have been utilized in application examples such as diode–less rectifier and inductance simulations, as well as low–pass, band–pass and universal filters. All active elements and application examples have been verified by PSpice simulator using the 0.18 m TSMC CMOS parameters. Sufficient numbers of simulated plots are included in this thesis to illustrate the precise and strong behavior of structures.

Speech Processing Front-end in Low-power Hardware

The objective of this work is to develop analog integrated circuits to serve as low-power auditory front-ends in signal processing systems. An analog front-end can be used for feature-extraction to reduce the requirements of the digital back-end, or to detect and call attention to compelling characteristics of a signal while the back-end is in sleep mode. Such a front-end should be advantageous for speech recognition, noise suppression, auditory scene analysis, hearing prostheses, biological modeling, or hardware-based event detection.;This work presents a spectral decomposition system, which consists of a bandpass filter bank with sub-band magnitude detection. The bandpass filter is low-power and each channel can be individually programmed for different quality factors and passband gains. The novel magnitude detector has a 68 decibel dynamic range, excellent tracking capability, and consumes less than a microwatt of power. The system, which was fabricated in a 0.18 micron process, consists of a 16-channel filter bank and a variety of sub-band computational elements

Front-end receiver for miniaturised ultrasound imaging

Point of care ultrasonography has been the focus of extensive research over the past few decades. Miniaturised, wireless systems have been envisaged for new application areas, such as capsule endoscopy, implantable ultrasound and wearable ultrasound. The hardware constraints of such small-scale systems are severe, and tradeoffs between power consumption, size, data bandwidth and cost must be carefully balanced. To address these challenges, two synthetic aperture receiver architectures are proposed and compared. The architectures target highly miniaturised, low cost, B-mode ultrasound imaging systems. The first architecture utilises quadrature (I/Q) sampling to minimise the signal bandwidth and computational load. Synthetic aperture beamforming is carried out using a single-channel, pipelined protocol in order to minimise system complexity and power consumption. A digital beamformer dynamically apodises and focuses the data by interpolating and applying complex phase rotations to the I/Q samples. The beamformer is implemented on a Spartan-6 FPGA and consumes 296mW for a frame rate of 7Hz. The second architecture employs compressive sensing within the finite rate of innovation (FRI) framework to further reduce the data bandwidth. Signals are sampled below the Nyquist frequency, and then transmitted to a digital back-end processor, which reconstructs I/Q components non-linearly, and then carries out synthetic aperture beamforming. Both architectures were tested in hardware using a single-channel analogue front-end (AFE) that was designed and fabricated in AMS 0.35μm CMOS. The AFE demodulates RF ultrasound signals sequentially into I/Q components, and comprises a low-noise preamplifier, mixer, programmable gain amplifier (PGA) and lowpass filter. A variable gain low noise preamplifier topology is used to enable quasi-exponential time-gain control (TGC). The PGA enables digital selection of three gain values (15dB, 22dB and 25.5dB). The bandwidth of the lowpass filter is also selectable between 1.85MHz, 510kHz and 195kHz to allow for testing of both architectural frameworks. The entire AFE consumes 7.8 mW and occupies an area of 1.5×1.5 mm. In addition to the AFE, this thesis also presents the design of a pseudodifferential, log-domain multiplier-filter or “multer” which demodulates low-RF signals in the current-domain. This circuit targets high impedance transducers such as capacitive micromachined ultrasound transducers (CMUTs) and offers a 20dB improvement in dynamic range over the voltage-mode AFE. The bandwidth is also electronically tunable. The circuit was implemented in 0.35μm BiCMOS and was simulated in Cadence; however, no fabrication results were obtained for this circuit. B-mode images were obtained for both architectures. The quadrature SAB method yields a higher image SNR and 9% lower root mean squared error with respect to the RF-beamformed reference image than the compressive SAB method. Thus, while both architectures achieve a significant reduction in sampling rate, system complexity and area, the quadrature SAB method achieves better image quality. Future work may involve the addition of multiple receiver channels and the development of an integrated system-on-chip.Open Acces

Nonlinearity and noise modeling of operational transconductance amplifiers for continuous time analog filters

A general framework for performance optimization of continuous-time OTA-C (Operational Transconductance Amplifier-Capacitor) filters is proposed. Efficient procedures for evaluating nonlinear distortion and noise valid for any filter of arbitrary order are developed based on the matrix description of a general OTA-C filter model . Since these procedures use OTA macromodels, they can be used to obtain the results significantly faster than transistor-level simulation. In the case of transient analysis, the speed-up may be as much as three orders of magnitude without almost no loss of accuracy. This makes it possible to carry out direct numerical optimization of OTA-C filters with respect to important characteristics such as noise performance, THD, IM3, DR or SNR. On the other hand, the general OTA-C filter model allows us to apply matrix transforms that manipulate (rescale) filter element values and/or change topology without changing its transfer function. The above features are a basis to build automated optimization procedures for OTA-C filters. In particular, a systematic optimization procedure using equivalence transformations is proposed. The research also proposes suitable software implementations of the optimization process. The first part of the research proposes a general performance optimization procedure and to verify the process two application type examples are mentioned. An application example of the proposed approach to optimal block sequencing and gain distribution of 8th order cascade Butterworth filter (for two variants of OTA topologies) is given. Secondly the modeling tool is used to select the best suitable topology for a 5th order Bessel Low Pass Filter. Theoretical results are verified by comparing to transistor-level simulation withCADENCE. For the purpose of verification, the filters have also been fabricated in standard 0.5mm CMOS process. The second part of the research proposes a new linearization technique to improve the linearity of an OTA using an Active Error Feedforward technique. Most present day applications require very high linear circuits combined with low noise and low power consumption. An OTA based biquad filter has also been fabricated in 0.35mm CMOS process. The measurement results for the filter and the stand alone OTA have been discussed. The research focuses on these issues