3次元型トランジスタを用いたLSIの設計法

Design technology of LSI such as system LSI ana memory using 3 dimensional transistors has been described. By using 3 dimensional transistors, FinFET, double gate transistor and stacked double gate transistor, pattern area of logic gate and full adder circuit can be reduced drastically compared with that with conventional planar transistor. By using double gate transistor and Carbon Nano Tube transistor the reconfigurable circuit with many logic functions can be realized with small pattern area. Furthermore, staked NAND MRAM with 3 dimensional spin transistor has been newly proposed. This stacked NAND MRAM is a promising candidate which replaces currently available DRAM and NAND flash memory.Design technology of LSI such as system LSI ana memory using 3 dimensional transistors has been described. By using 3 dimensional transistors, FinFET, double gate transistor and stacked double gate transistor, pattern area of logic gate and full adder circuit can be reduced drastically compared with that with conventional planar transistor. By using double gate transistor and Carbon Nano Tube transistor the reconfigurable circuit with many logic functions can be realized with small pattern area. Furthermore, staked NAND MRAM with 3 dimensional spin transistor has been newly proposed. This stacked NAND MRAM is a promising candidate which replaces currently available DRAM and NAND flash memory

Speculative Segmented Sum for Sparse Matrix-Vector Multiplication on Heterogeneous Processors

Sparse matrix-vector multiplication (SpMV) is a central building block for scientific software and graph applications. Recently, heterogeneous processors composed of different types of cores attracted much attention because of their flexible core configuration and high energy efficiency. In this paper, we propose a compressed sparse row (CSR) format based SpMV algorithm utilizing both types of cores in a CPU-GPU heterogeneous processor. We first speculatively execute segmented sum operations on the GPU part of a heterogeneous processor and generate a possibly incorrect results. Then the CPU part of the same chip is triggered to re-arrange the predicted partial sums for a correct resulting vector. On three heterogeneous processors from Intel, AMD and nVidia, using 20 sparse matrices as a benchmark suite, the experimental results show that our method obtains significant performance improvement over the best existing CSR-based SpMV algorithms. The source code of this work is downloadable at https://github.com/bhSPARSE/Benchmark_SpMV_using_CSRComment: 22 pages, 8 figures, Published at Parallel Computing (PARCO

Six decades of research on 2D materials: progress, dead ends, and new horizons

The present paper guides the reader through six decades of research on 2D materials, thereby putting special focus on the use of these materials for electronic devices. It is shown that after a slow start and only little activity over many years, since 2004 the exploration of 2D materials advanced at an enormous pace. While some of the high expectations raised in the so-called golden era of graphene did not fulfil, other electronic applications for 2D materials that originally were not on the agenda gain increasing attention now. One of the main research topics in the field of 2D materials during the early 2000s was high-performance graphene transistors. This effort, however, led to a dead end due the consequences of the missing bandgap in graphene. On the other hand, the semiconducting 2D materials show potential for different device concepts including stacked-channel 2D nanosheet MOSFETs and 2D memristors. The former may become the transistor architecture of choice at the end of the CMOS roadmap and 2D memristors represent a promising device concept for future neuromorphic computing, a type of information processing that shows great potential for artificial intelligence applications where energy efficiency is a key requirement

Concertina: Squeezing in cache content to operate at near-threshold voltage

© 2015 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.Scaling supply voltage to values near the threshold voltage allows a dramatic decrease in the power consumption of processors; however, the lower the voltage, the higher the sensitivity to process variation, and, hence, the lower the reliability. Large SRAM structures, like the last-level cache (LLC), are extremely vulnerable to process variation because they are aggressively sized to satisfy high density requirements. In this paper, we propose Concertina, an LLC designed to enable reliable operation at low voltages with conventional SRAM cells. Based on the observation that for many applications the LLC contains large amounts of null data, Concertina compresses cache blocks in order that they can be allocated to cache entries with faulty cells, enabling use of 100 percent of the LLC capacity. To distribute blocks among cache entries, Concertina implements a compression- and fault-aware insertion/replacement policy that reduces the LLC miss rate. Concertina reaches the performance of an ideal system implementing an LLC that does not suffer from parameter variation with a modest storage overhead. Specifically, performance degrades by less than 2 percent, even when using small SRAM cells, which implies over 90 percent of cache entries having defective cells, and this represents a notable improvement on previously proposed techniques.Peer ReviewedPostprint (author's final draft

Heterogeneous CPU/GPU Memory Hierarchy Analysis and Optimization

In this master thesis, we propose a scheduling reordering for heterogeneous processors based on a hysteresis detector to give some fairness and speedup to the memory request threads taking advantage of the bank level parallelism at the memory system organization

Characterization of RTN in FD-SOI transistor

The project focuses on the study of transistors with FD-SOI technology to provide and corroborate information on their degradation when applying Bia Temperature Instability (BTI) and Channel Hot Carriers (HCC). Applying the constant voltage stress technique to the devices, observing how their behaviour evolves during their useful life, in addition to focusing the study on random telegraph noise (RTN). The results of the fresh and stressed characterization of the devices are compared to know how the transistors vary after different stress tensions from the characteristic IG-VG, ID-VG and ID-VD. From the method of time lag plot (W-TLP) it is possible to identify the relevant levels of RTN in which the devices work in fresh and stressed state. The conclusion is that the effects of degradation in this technology affect their operation and provide an increase in the RTN in the devices