24GHz CMOS direct downconversion receiver front-end and VCO design

Because of advancements in RF CMOS circuits, devices, and passive elements in the last decade, it has become possible to develop a RF system-on-chip (SoC) that integrates RF, analog and digital circuits completely. Direct downconversion, or zero-IF downconversion architecture, shows an advantage over traditional superheterodyne architectures, because it eliminates the image rejection filter and IF filter, and employs only one local oscillator (LO), which reduces the receiver size and power dissipation significantly. For this reason, direct downconversion has drawn more and more attention recently in various wireless applications. However, it also presents some design challenges like flicker noise, DC offsets, even-order distortion, and I/Q mismatches. In this work, a thorough noise analysis and a comprehensive study of the noise mechanism of the low noise amplifier of CMOS direct downconversion receivers (DCR) is given. Also addressed is the design of a cross-coupled LC voltage-controlled oscillator (VCO). For the low noise amplifier, which presents major noise contribution to the DCR front-end, an optimization technique which employs both a parallel capacitance and an inter-stage inductor is proposed. The addition of this capacitance helps keep the active device relatively small, and the analysis on the effects of the inter-stage inductor shows that it helps boost gain of the LNA at the desired operation frequency of 2.4GHz, and offers a lower noise figure. In order to achieve direct downconversion, both a passive switching mixer and an active double-balanced mixer are presented. The passive switching mixer helps solve the problem of flicker noise, but suffers power loss, while the double-balanced architecture helps relieve the problems of DC offset and second-order distortion. The last part of this presentation is about a partially tunable CMOS LC-VCO which achieves good phase noise performance at the cost of smaller tuning range. It uses on-chip spiral inductors and junction varactors in the resonant LC-tank. The presented building blocks can be used for a low-power, low-voltage DCR front-end for 802.11b/g applications. It is concluded that direct downconversion architecture can find its use in low-power, low-cost 802.11b and Bluetooth applications should the circuit design make use of the optimization techniques addressed in this work

Investigation on LIGA-MEMS and on-chip CMOS capacitors for a VCO application

Modern communication systems require high performance radio frequency (RF) and microwave circuits and devices. This is becoming increasingly challenging to realize in the content of cost/size constraints. Integrated circuits (ICs) satisfy the cost/size requirement, but performance is often sacri¯ced. For instance, high quality factor (Q factor) passive components are difficult to achieve in standard silicon-based IC processes.In recent years, microelectromechanical systems (MEMS) devices have been receiving increasing attention as a possible replacement for various on-chip passive elements, offering potential improvement in performance while maintaining high levels of integration. Variable capacitors (varactor) are common elements used in various applications. One of the MEMS variable capacitors that has been recently developed is built using deep X-ray lithography (as part of the LIGA process). This type of capacitor exhibits high quality factor at microwave frequencies.The complementary metal oxide semiconductor (CMOS) technology dominates the silicon IC process. CMOS becomes increasingly popular for RF applications due to its advantages in level of integration, cost and power consumption. This research demonstrates a CMOS voltage-controlled oscillator (VCO) design which is used to investigate methods, advantages and problems in integrating LIGA-MEMS devices to CMOS RF circuits, and to evaluate the performance of the LIGA-MEMS variable capacitor in comparison with the conventional on-chip CMOS varactor. The VCO was designed and fabricated using TSMC 0.18 micron CMOS technology. The core of the VCO, including transistors, resistors, and on-chip inductors was designed to connect to either an on-chip CMOS varactor or an off-chip LIGA-MEMS capacitor to oscillate between 2.6 GHz and 2.7 GHz. Oscillator phase noise analysis is used to compare the performance between the two capacitors. The fabricated VCO occupied an area of 1 mm^2.This initial attempt at VCO fabrication did not produce a functional VCO, so the performance of the capacitors with the fabricated VCO could not be tested. However, the simulation results show that with this LIGA-MEMS capacitor, a 6.4 dB of phase noise improvement at 300 kHz offset from the carrier is possible in a CMOS-based VCO design

Realization of a voltage controlled oscillator using 0.35 um sige-bicmos technology for multi-band applications

The stable growth in wireless communications market has engendered the interoperability of various standards in a single broadband frequency range from hundred MHz up to several GHz. This frequency range consists of various wireless applications such as GSM, Bluetooth and WLAN. Therefore, an agile wireless system needs smart RF front-ends for functioning properly in such a crowded spectrum. As a result, the demand for multi-standard RF transceivers which put various wireless and cordless phone standards together in one structure was increased. The demand for multi-standard RF transceivers gives a key role to reconfigurable wideband VCO operation with low-power and low-phase noise characteristics. Besides agility and intelligence, such a communication system (GSM, WLAN, Global Positioning Systems, etc. ) required meeting the requirements of several standards in a cost-effective way. This, when cost and integration are the major concerns, leads to the exploitation of Si-based technologies. In this thesis, an integrated 2.2-5.7GHz Multi-band differential LC VCO for Multi-standard Wireless Communication systems was designed utilizing 0.35μm SiGe BiCMOS technology. The topology, which combines the switching inductors and capacitors together in the same circuit, is a novel approach for wideband VCOs. Based on the post layout simulation results, the VCO can be tuned using a DC voltage of 0 to 3.3V for 5 different frequency bands (2.27-2.51 GHz, 2.48-2.78GHz, 3.22-3.53GHz, 3.48-3.91GHz and 4.528-5.7GHz) with a maximum bandwidth of 1.36GHz and a minimum bandwidth of 300MHz. The designed and simulated VCO can generate a differential output power between 0.992 dBm and -6.087 dBm with an average power consumption of 44.21mW including the buffers. The average second and third harmonics level were obtained as -37.21 dBm and -47.6 dBm, respectively. The phase noise between -110.45 and -122.5 dBc/Hz, that was simulated at 1 MHz offset, can be obtained through the frequency of interest. Additionally, the figure of merit (FOM), that includes all important parameters such as the phase noise, the power consumption and the ratio of the operating frequency to the offset frequency, is between -176.48 and -181.16 and comparable or better than the ones with the other current VCOs. The main advantage of this study in comparison with the other VCOs, is covering 5 frequency bands starting from 2.27 up to 5.76 GHz without FOM and area abandonment

Design and implementation of a frequency synthesizer for an IEEE 802.15.4/Zigbee transceiver

The frequency synthesizer, which performs the main role of carrier generation for the down-conversion/up-conversion operations, is a key building block in radio transceiver front-ends. The design of a synthesizer for a 2.4 GHz IEEE 802.15.4/Zigbee transceiver forms the core of this work. This thesis provides a step-by-step procedure for the design of a frequency synthesizer in a transceiver environment, from the mapping of standard-specifications to its integrated circuit implementation in a CMOS technology. The results show that careful system level planning leads to high-performance realizations of the synthesizer. A strategy of using different supply voltages to enhance the performance of each building block is discussed. A section is presented on layout and board level issues, especially for radio-frequency systems, and their effect on synthesizer performance. The synthesizer consumes 15.5 mW and meets the specifications of the 2.4 GHz IEEE 802.15.4/Zigbee standard. It is capable of 5 GHz operation with a VCO sensitivity of 135 MHz/V and a tuning range of 700 MHz. It can be seen that the adopted methodology can be used for the design of high-performance frequency synthesizers for any narrow-band wireless standard

Design of CMOS LC voltage controlled oscillators

This work presents the design and implementation of CMOS LC voltage controlled oscillators. On-chip planar spiral inductors and PMOS inversion mode varactors were utilized to implement the resonator. Two voltage controlled oscillators (VCOs) were realized as a part of this work, one designed to operate at 1.1 GHz while the second at 1.8 GHz. Both VCOs were implemented in a scalable digital CMOS process, with the former in a 1.5 micron CMOS process and the latter in a 0.5 micron technology. A simulation based methodology was adopted to arrive at a simple pi model used to model the metal and substrate related losses responsible for deteriorating the integrated inductor\u27s performance. Geometry based optimization techniques were utilized to arrive at an inductor geometry that ensures reasonable quality factor. In addition to the core VCO structure a host of test structures have been incorporated in order to carry out two-port network measurements in the future. Such measurements should enable one to gain a greater insight into the integrated inductor and varactor\u27s performance

Design And Implementation Of Up-Conversion Mixer And Lc-Quadrature Oscillator For IEEE 802.11a WLAN Transmitter Application Utilizing 0.18 Pm CMOS Technology [TK7871.99.M44 H279 2008 f rb].

Perlumbaan implementasi litar terkamil radio, dengan kos yang rendah telah menggalakkan penggunaan teknologi CMOS. The drive for cost reduction has led to the use of CMOS technology for highly integrated radios

Integrated RF oscillators and LO signal generation circuits

This thesis deals with fully integrated LC oscillators and local oscillator (LO) signal generation circuits. In communication systems a good-quality LO signal for up- and down-conversion in transmitters is needed. The LO signal needs to span the required frequency range and have good frequency stability and low phase noise. Furthermore, most modern systems require accurate quadrature (IQ) LO signals. This thesis tackles these challenges by presenting a detailed study of LC oscillators, monolithic elements for good-quality LC resonators, and circuits for IQ-signal generation and for frequency conversion, as well as many experimental circuits. Monolithic coils and variable capacitors are essential, and this thesis deals with good structures of these devices and their proper modeling. As experimental test devices, over forty monolithic inductors and thirty varactors have been implemented, measured and modeled. Actively synthesized reactive elements were studied as replacements for these passive devices. At first glance these circuits show promising characteristics, but closer noise and nonlinearity analysis reveals that these circuits suffer from high noise levels and a small dynamic range. Nine circuit implementations with various actively synthesized variable capacitors were done. Quadrature signal generation can be performed with three different methods, and these are analyzed in the thesis. Frequency conversion circuits are used for alleviating coupling problems or to expand the number of frequency bands covered. The thesis includes an analysis of single-sideband mixing, frequency dividers, and frequency multipliers, which are used to perform the four basic arithmetical operations for the frequency tone. Two design cases are presented. The first one is a single-sideband mixing method for the generation of WiMedia UWB LO-signals, and the second one is a frequency conversion unit for a digital period synthesizer. The last part of the thesis presents five research projects. In the first one a temperature-compensated GaAs MESFET VCO was developed. The second one deals with circuit and device development for an experimental-level BiCMOS process. A cable-modem RF tuner IC using a SiGe process was developed in the third project, and a CMOS flip-chip VCO module in the fourth one. Finally, two frequency synthesizers for UWB radios are presented

Design and implementation of fully integrated low-voltage low-noise CMOS VCO.

Yip Kim-fung.Thesis (M.Phil.)--Chinese University of Hong Kong, 2002.Includes bibliographical references (leaves 95-100).Abstracts in English and Chinese.Abstract --- p.IAcknowledgement --- p.IIITable of Contents --- p.IVChapter Chapter 1 --- Introduction --- p.1Chapter 1.1 --- Motivation --- p.1Chapter 1.2 --- Objective --- p.6Chapter Chapter 2 --- Theory of Oscillators --- p.7Chapter 2.1 --- Oscillator Design --- p.7Chapter 2.1.1 --- Loop-Gain Method --- p.7Chapter 2.1.2 --- Negative Resistance-Conductance Method --- p.8Chapter 2.1.3 --- Crossed-Coupled Oscillator --- p.10Chapter Chapter 3 --- Noise Analysis --- p.15Chapter 3.1 --- Origin of Noise Sources --- p.16Chapter 3.1.1 --- Flicker Noise --- p.16Chapter 3.1.2 --- Thermal Noise --- p.17Chapter 3.1.3 --- Noise Model of Varactor --- p.18Chapter 3.1.4 --- Noise Model of Spiral Inductor --- p.19Chapter 3.2 --- Derivation of Resonator --- p.19Chapter 3.3 --- Phase Noise Model --- p.22Chapter 3.3.1 --- Leeson's Model --- p.23Chapter 3.3.2 --- Phase Noise Model defined by J. Cranincks and M Steyaert --- p.24Chapter 3.3.3 --- Non-linear Analysis of Phase Noise --- p.26Chapter 3.3.4 --- Flicker-Noise Upconversion Mechanism --- p.31Chapter 3.4 --- Phase Noise Reduction Techniques --- p.33Chapter 3.4.1 --- Conventional Tank Circuit Structure --- p.33Chapter 3.4.2 --- Enhanced Q tank circuit Structure --- p.35Chapter 3.4.3 --- Tank Circuit with parasitics --- p.37Chapter 3.4.4 --- Reduction of Up-converted Noise --- p.39Chapter Chapter 4 --- CMOS Technology and Device Modeling --- p.42Chapter 4.1 --- Device Modeling --- p.42Chapter 4.1.1 --- FET model --- p.42Chapter 4.1.2 --- Layout of Interdigitated FET --- p.46Chapter 4.1.3 --- Planar Inductor --- p.48Chapter 4.1.4 --- Circuit Model of Planar Inductor --- p.50Chapter 4.1.5 --- Inductor Layout Consideration --- p.54Chapter 4.1.6 --- CMOS RF Varactor --- p.55Chapter 4.1.7 --- Parasitics of PMOS-type varactor --- p.57Chapter Chapter 5 --- Design of Integrated CMOS VCOs --- p.59Chapter 5.1 --- 1.5GHz CMOS VCO Design --- p.59Chapter 5.1.1 --- Equivalent circuit model of differential LC VCO --- p.59Chapter 5.1.2 --- Reference Oscillator Circuit --- p.61Chapter 5.1.3 --- Proposed Oscillator Circuit --- p.62Chapter 5.1.4 --- Output buffer --- p.63Chapter 5.1.5 --- Biasing Circuitry --- p.64Chapter 5.2 --- Spiral Inductor Design --- p.65Chapter 5.3 --- Determination of W/L ratio of FET --- p.67Chapter 5.4 --- Varactor Design --- p.68Chapter 5.5 --- Layout (Cadence) --- p.69Chapter 5.6 --- Circuit Simulation (SpectreRF) --- p.74Chapter Chapter 6 --- Experimental Results and Discussion --- p.76Chapter 6.1 --- Measurement Setup --- p.76Chapter 6.2 --- Measurement results: Reference Oscillator Circuit --- p.81Chapter 6.2.1 --- Output Spectrum --- p.81Chapter 6.2.2 --- Phase Noise Performance --- p.82Chapter 6.2.3 --- Tuning Characteristic --- p.83Chapter 6.2.4 --- Microphotograph --- p.84Chapter 6.3 --- Measurement results: Proposed Oscillator Circuit --- p.85Chapter 6.3.1 --- Output Spectrum --- p.85Chapter 6.3.2 --- Phase Noise Performance --- p.86Chapter 6.3.3 --- Tuning Characteristic --- p.87Chapter 6.3.4 --- Microphotograph --- p.88Chapter 6.4 --- Comparison of Measured Results --- p.89Chapter 6.4.1 --- Phase Noise Performance --- p.89Chapter 6.4.2 --- Tuning Characteristic --- p.90Chapter Chapter 7 --- Conclusion and Future Work --- p.93Chapter 7.1 --- Conclusion --- p.93Chapter 7.2 --- Future Work --- p.94References --- p.95Author's Publication --- p.100Appendix A --- p.101Appendix B --- p.104Appendix C --- p.10