Design Considerations of a Sub-50 {\mu}W Receiver Front-end for Implantable Devices in MedRadio Band

Emerging health-monitor applications, such as information transmission through multi-channel neural implants, image and video communication from inside the body etc., calls for ultra-low active power (<50${\mu}$W) high data-rate, energy-scalable, highly energy-efficient (pJ/bit) radios. Previous literature has strongly focused on low average power duty-cycled radios or low power but low-date radios. In this paper, we investigate power performance trade-off of each front-end component in a conventional radio including active matching, down-conversion and RF/IF amplification and prioritize them based on highest performance/energy metric. The analysis reveals 50${\Omega}$ active matching and RF gain is prohibitive for 50${\mu}$W power-budget. A mixer-first architecture with an N-path mixer and a self-biased inverter based baseband LNA, designed in TSMC 65nm technology show that sub 50${\mu}$W performance can be achieved up to 10Mbps (< 5pJ/b) with OOK modulation.Comment: Accepted to appear on International Conference on VLSI Design 2018 (VLSID

Efficient and Interference-Resilient Wireless Connectivity for IoT Applications

With the coming of age of the Internet of Things (IoT), demand on ultra-low power (ULP) and low-cost radios will continue to boost tremendously. The Bluetooth-Low-energy (BLE) standard provides a low power solution to connect IoT nodes with mobile devices, however, the power of maintaining a connection with a reasonable latency remains the limiting factor in defining the lifetime of event-driven BLE devices. BLE radio power consumption is in the milliwatt range and can be duty cycled for average powers around 30μW, but at the expense of long latency. Furthermore, wireless transceivers traditionally perform local oscillator (LO) calibration using an external crystal oscillator (XTAL) that adds significant size and cost to a system. Removing the XTAL enables a true single-chip radio, but an alternate means for calibrating the LO is required. Innovations in both the system architecture and circuits implementation are essential for the design of truly ubiquitous receivers for IoT applications. This research presents two porotypes as back-channel BLE receivers, which have lower power consumption while still being robust in the presents of interference and able to receive back-channel message from BLE compliant transmitters. In addition, the first crystal-less transmitter with symmetric over-the-air clock recovery compliant with the BLE standard using a GFSK-Modulated BLE Packet is presented.PHDElectrical and Computer EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/162942/1/abdulalg_1.pd

Millimeter-Scale and Energy-Efficient RF Wireless System

This dissertation focuses on energy-efficient RF wireless system with millimeter-scale dimension, expanding the potential use cases of millimeter-scale computing devices. It is challenging to develop RF wireless system in such constrained space. First, millimeter-sized antennae are electrically-small, resulting in low antenna efficiency. Second, their energy source is very limited due to the small battery and/or energy harvester. Third, it is required to eliminate most or all off-chip devices to further reduce system dimension. In this dissertation, these challenges are explored and analyzed, and new methods are proposed to solve them. Three prototype RF systems were implemented for demonstration and verification. The first prototype is a 10 cubic-mm inductive-coupled radio system that can be implanted through a syringe, aimed at healthcare applications with constrained space. The second prototype is a 3x3x3 mm far-field 915MHz radio system with 20-meter NLOS range in indoor environment. The third prototype is a low-power BLE transmitter using 3.5x3.5 mm planar loop antenna, enabling millimeter-scale sensors to connect with ubiquitous IoT BLE-compliant devices. The work presented in this dissertation improves use cases of millimeter-scale computers by presenting new methods for improving energy efficiency of wireless radio system with extremely small dimensions. The impact is significant in the age of IoT when everything will be connected in daily life.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/147686/1/yaoshi_1.pd

A -5 dBm 400MHz OOK Transmitter for Wireless Medical Application

A 400 MHz high efficiency transmitter forwireless medical application is presented in this paper. Transmitter architecture with high-energy efficiencies isproposed to achieve high data rate with low powerconsumption. In the on-off keying transmitters, the oscillatorand power amplifier are turned off when the transmittersends 0 data. The proposed class-e power amplifier has highefficiency for low level output power. The proposed on-offkeying transmitter consumes 1.52 mw at -5 dBm output by 40Mbps data rate and energy consumption 38 pJ/bit. Theproposed transmitter has been designed in 0.18µm CMOStechnology

Integrated Circuit and System Design for Cognitive Radio and Ultra-Low Power Applications

The ubiquitous presence of wireless and battery-powered devices is an inseparable and invincible feature of our modern life. Meanwhile, the spectrum aggregation, and limited battery capacity of handheld devices challenge the exploding demand and growth of such radio systems. In this work, we try to present two separate solutions for each case; an ultra-wideband (UWB) receiver for Cognitive Radio (CR) applications to deal with spectrum aggregation, and an ultra-low power (ULP) receiver to enhance battery life of handheld wireless devices. Limited linearity and LO harmonics mixing are two major issues that ultra-wideband receivers, and CR in particular, are dealing with. Direct conversion schemes, based on current-driven passive mixers, have shown to improve the linearity, but unable to resolve LO harmonic mixing problem. They are usually limited to 3rd, and 5th harmonics rejection or require very complex and power hungry circuitry for higher number of harmonics. This work presents a heterodyne up-down conversion scheme in 180 nm CMOS technology for CR applications (54-862 MHz band) that mitigates the harmonic mixing issue for all the harmonics, while by employing an active feedback loop, a comparable to the state-of-the art IIP3 of better than +10 dBm is achieved. Measurements show an average NF of 7.5 dB when the active feedback loop is off (i.e. in the absence of destructive interference), and 15.5 dB when the feedback loop is active and a 0 dBm interferer is applied, respectively. Also, the second part of this work presents an ultra-low power super-regenerative receiver (SRR) suitable for OOK modulation and provides analytical insight into its design procedure. The receiver is fabricated in 40 nm CMOS technology and operates in the ISM band of 902-928 MHz. Binary search algorithm through Successive Approximation Register (SAR) architecture is being exploited to calibrate the internally generated quench signal and the working frequency of the receiver. Employing an on-chip inductor and a single-ended to differential architecture for the input amplifier has made the receiver fully integrable, eliminating the need for external components. A power consumption of 320 µW from a 0.65 V supply results in an excellent energy efficiency of 80 pJ/b at 4 Mb/s data rate. The receiver also employs an ADC that enables soft-decisioning and a convenient sensitivity-data rate trade-off, achieving sensitivity of -86.5, and -101.5 dBm at 1000 and 31.25 kbps data rate, respectivel

Integrated Circuit and System Design for Cognitive Radio and Ultra-Low Power Applications

The ubiquitous presence of wireless and battery-powered devices is an inseparable and invincible feature of our modern life. Meanwhile, the spectrum aggregation, and limited battery capacity of handheld devices challenge the exploding demand and growth of such radio systems. In this work, we try to present two separate solutions for each case; an ultra-wideband (UWB) receiver for Cognitive Radio (CR) applications to deal with spectrum aggregation, and an ultra-low power (ULP) receiver to enhance battery life of handheld wireless devices. Limited linearity and LO harmonics mixing are two major issues that ultra-wideband receivers, and CR in particular, are dealing with. Direct conversion schemes, based on current-driven passive mixers, have shown to improve the linearity, but unable to resolve LO harmonic mixing problem. They are usually limited to 3rd, and 5th harmonics rejection or require very complex and power hungry circuitry for higher number of harmonics. This work presents a heterodyne up-down conversion scheme in 180 nm CMOS technology for CR applications (54-862 MHz band) that mitigates the harmonic mixing issue for all the harmonics, while by employing an active feedback loop, a comparable to the state-of-the art IIP3 of better than +10 dBm is achieved. Measurements show an average NF of 7.5 dB when the active feedback loop is off (i.e. in the absence of destructive interference), and 15.5 dB when the feedback loop is active and a 0 dBm interferer is applied, respectively. Also, the second part of this work presents an ultra-low power super-regenerative receiver (SRR) suitable for OOK modulation and provides analytical insight into its design procedure. The receiver is fabricated in 40 nm CMOS technology and operates in the ISM band of 902-928 MHz. Binary search algorithm through Successive Approximation Register (SAR) architecture is being exploited to calibrate the internally generated quench signal and the working frequency of the receiver. Employing an on-chip inductor and a single-ended to differential architecture for the input amplifier has made the receiver fully integrable, eliminating the need for external components. A power consumption of 320 µW from a 0.65 V supply results in an excellent energy efficiency of 80 pJ/b at 4 Mb/s data rate. The receiver also employs an ADC that enables soft-decisioning and a convenient sensitivity-data rate trade-off, achieving sensitivity of -86.5, and -101.5 dBm at 1000 and 31.25 kbps data rate, respectivel

Ultra-low power, low-voltage transmitter at ISM band for short range transceivers

Tezin basılısı İstanbul Şehir Üniversitesi Kütüphanesi'ndedir.The increasing demand for technology to be used in every aspect of our lives has led the way to many new applications and communication standards. WSN and BAN are some of the new examples that utilize electronic circuit design in the form of very small sensors to perform their applications. They consist of small sensor nodes and have applications ranging from entertainment to medicine. Requirements such as decreasing the area and the power consumption help to have longer-lasting batteries and smaller devices. The standard paves the way for the devices from different vendors to communicate with each other, and that motivates us to make designs as compatible with the standard as it can be. In this thesis, an ultra-low power high efficient transmitter with a small area working at 2.4 GHz have been designed for BAN applications. A study on the system-view perspective is important in optimizing the area and power since the transmitter architecture can change the circuit design. From a circuit design perspective, seeking to decrease power consumption means thinking of new techniques to implement the same function or a new system. Inspired by new trends, this research presents a design solution to the previously mentioned problem and hopefully, after fabrication, the measured results will match the simulated results to prove the validity of the design.Declaration of Authorship ii Abstract iv Öz v Acknowledgments vii List of Figures x List of Tables xiii Abbreviations xiv 1 Introduction 1 1.1 Background and Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 Communication Concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2.1 Digital Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.2.2 Unwanted Power Limitations . . . . . . . . . . . . . . . . . . . . . 3 1.2.3 Multiple Access Techniques . . . . . . . . . . . . . . . . . . . . . . 3 1.3 Transmitter System Level Specifications . . . . . . . . . . . . . . . . . . . 4 1.3.1 Low Power Wireless Standards . . . . . . . . . . . . . . . . . . . . 4 1.4 Low-Power Wireless Transceiver systems . . . . . . . . . . . . . . . . . . . 6 1.4.1 Survey of the previous work . . . . . . . . . . . . . . . . . . . . . . 7 1.4.2 The Designed Transmitter System . . . . . . . . . . . . . . . . . . 8 1.5 Ultra-Low Power Transmitters Performance Metrics . . . . . . . . . . . . 9 1.6 Thesis Contribution and Outline . . . . . . . . . . . . . . . . . . . . . . . 10 2 Circuit Design for The Transmitter 11 2.1 Technology Characterization and Modeling for Low-Power Designs . . . 11 2.1.1 Passive Components modeling . . . . . . . . . . . . . . . . . . . . 11 2.1.2 Active Components Modeling . . . . . . . . . . . . . . . . . . . . . 13 2.1.3 MOS Transistor Sub-threshold Modeling . . . . . . . . . . . . . . 13 2.1.4 MOS Transistor Simulation-Based Modeling . . . . . . . . . . . . . 14 2.2 Low-Voltage Low-Power Analog and RF Design Principles . . . . . . . . . 17 2.2.1 Separate Gate Biasing of The Inverter . . . . . . . . . . . . . . . . 17 2.2.2 Body Biasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3 Low-Voltage Analog Mixed Biasing Circuit Designs . . . . . . . . . . . . . 18 2.3.1 DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.3.2 Operational Amplifier Design . . . . . . . . . . . . . . . . . . . . . 19 2.4 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.4.1 The MEMS Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.4.2 Crystal Oscillator Topologies . . . . . . . . . . . . . . . . . . . . . 23 2.4.3 Design of The CMOS Crystal Oscillator . . . . . . . . . . . . . . . 26 2.5 Pre-Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.6 OOK Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.7 BPSK Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.8 Digital Control of the Modulators . . . . . . . . . . . . . . . . . . . . . . . 35 2.9 Power Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 2.9.1 ULP PA Topologies Survey . . . . . . . . . . . . . . . . . . . . . . 38 2.9.2 The Push-Pull PA Design Methodology . . . . . . . . . . . . . . . 41 2.10 Transmit/Receive (T/R) Switch . . . . . . . . . . . . . . . . . . . . . . . 43 2.10.1 T/R Switch Topologies . . . . . . . . . . . . . . . . . . . . . . . . . 43 2.10.2 Suggested Low-Area Low-Voltage RF Switch . . . . . . . . . . . . 46 3 Transmitter Integration and Final Results 48 3.1 Transmitter Simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.2 Transmitter Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 3.3 Results Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 3.4 Results Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 4 Conclusions 59 4.1 Thesis Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 A Bond Wire Parasitic Modeling 61 B Crystal Oscillator With Parasitic Effects 67 B.1 Simulation of FBAR with Parasitic Effects . . . . . . . . . . . . . . . . . 67 B.2 Root Locus Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Bibliography 7

Toward Brain Area Sensor Wireless Network

RÉSUMÉ De nouvelles approches d'interfaçage neuronal de haute performance sont requises pour les interfaces cerveau-machine (BMI) actuelles. Cela nécessite des capacités d'enregistrement/stimulation performantes en termes de vitesse, qualité et quantité, c’est à dire une bande passante à fréquence plus élevée, une résolution spatiale, un signal sur bruit et une zone plus large pour l'interface avec le cortex cérébral. Dans ce mémoire, nous parlons de l'idée générale proposant une méthode d'interfaçage neuronal qui, en comparaison avec l'électroencéphalographie (EEG), l'électrocorticographie (ECoG) et les méthodes d'interfaçage intracortical conventionnelles à une seule unité, offre de meilleures caractéristiques pour implémenter des IMC plus performants. Les avantages de la nouvelle approche sont 1) une résolution spatiale plus élevée - en dessous dumillimètre, et une qualité de signal plus élevée - en termes de rapport signal sur bruit et de contenu fréquentiel - comparé aux méthodes EEG et ECoG; 2) un caractère moins invasif que l'ECoG où l'enlèvement du crâne sous une opération d'enregistrement / stimulation est nécessaire; 3) une plus grande faisabilité de la libre circulation du patient à l'étude - par rapport aux deux méthodes EEG et ECoG où de nombreux fils sont connectés au patient en cours d'opération; 4) une utilisation à long terme puisque l'interface implantable est sans fil - par rapport aux deux méthodes EEG et ECoG qui offrent des temps limités de fonctionnement. Nous présentons l'architecture d'un réseau sans fil de microsystèmes implantables, que nous appelons Brain Area Sensor NETwork (Brain-ASNET). Il y a deux défis principaux dans la réalisation du projet Brain-ASNET. 1) la conception et la mise en oeuvre d'un émetteur-récepteur RF de faible consommation compatible avec la puce de capteurs de réseau implantable, et, 2) la conception d'un protocole de réseau de capteurs sans fil (WSN) ad-hoc économe en énergie. Dans ce mémoire, nous présentons un protocole de réseau ad-hoc économe en énergie pour le réseau désiré, ainsi qu'un procédé pour surmonter le problème de la longueur de paquet variable causé par le processus de remplissage de bit dans le protocole HDLC standard. Le protocole adhoc proposé conçu pour Brain-ASNET présente une meilleure efficacité énergétique par rapport aux protocoles standards tels que ZigBee, Bluetooth et Wi-Fi ainsi que des protocoles ad-hoc de pointe. Le protocole a été conçu et testé par MATLAB et Simulink.----------ABSTRACT New high-performance neural interfacing approaches are demanded for today’s Brain-Machine Interfaces (BMI). This requires high-performance recording/stimulation capabilities in terms of speed, quality, and quantity, i.e. higher frequency bandwidth, spatial resolution, signal-to-noise, and wider area to interface with the cerebral cortex. In this thesis, we talk about the general proposed idea of a neural interfacing method which in comparison with Electroencephalography (EEG), Electrocorticography (ECoG), and, conventional Single-Unit Intracortical neural interfacing methods offers better features to implement higher-performance BMIs. The new approach advantages are 1) higher spatial resolution – down to sub-millimeter, and higher signal quality − in terms of signal-to-noise ratio and frequency content − compared to both EEG and ECoG methods. 2) being less invasive than ECoG where skull removal Under recording/stimulation surgery is required. 3) higher feasibility of freely movement of patient under study − compared to both EEG and ECoG methods where lots of wires are connected to the patient under operation. 4) long-term usage as the implantable interface is wireless − compared to both EEG and ECoG methods where it is practical for only a limited time under operation. We present the architecture of a wireless network of implantable microsystems, which we call it Brain Area Sensor NETwork (Brain-ASNET). There are two main challenges in realization of the proposed Brain-ASNET. 1) design and implementation of power-hungry RF transceiver of the implantable network sensors' chip, and, 2) design of an energy-efficient ad-hoc Wireless Sensor Network (WSN) protocol. In this thesis, we introduce an energy-efficient ad-hoc network protocol for the desired network, along with a method to overcome the issue of variable packet length caused by bit stuffing process in standard HDLC protocol. The proposed ad-hoc protocol designed for Brain-ASNET shows better energy-efficiency compared to standard protocols like ZigBee, Bluetooth, and Wi-Fi as well as state-of-the-art ad-hoc protocols. The protocol was designed and tested by MATLAB and Simulink

A Sub-nW 2.4 GHz Transmitter for Low Data-Rate Sensing Applications

This paper presents the design of a narrowband transmitter and antenna system that achieves an average power consumption of 78 pW when operating at a duty-cycled data rate of 1 bps. Fabricated in a 0.18 μm CMOS process, the transmitter employs a direct-RF power oscillator topology where a loop antenna acts as a both a radiative and resonant element. The low-complexity single-stage architecture, in combination with aggressive power gating techniques and sizing optimizations, limited the standby power of the transmitter to only 39.7 pW at 0.8 V. Supporting both OOK and FSK modulations at 2.4 GHz, the transmitter consumed as low as 38 pJ/bit at an active-mode data rate of 5 Mbps. The loop antenna and integrated diodes were also used as part of a wireless power transfer receiver in order to kick-start the system power supply prior to energy harvesting operation.Semiconductor Research Corporation. Interconnect Focus CenterSemiconductor Research Corporation. C2S2 Focus CenterNational Institutes of Health (U.S.) (Grant K08 DC010419)National Institutes of Health (U.S.) (Grant T32 DC00038)Bertarelli Foundatio

Bidirectional Wireless Telemetry for High Channel Count Optogenetic Microsystems

In the past few decades, there has been a significant progress in the development of wireless data transmission systems, from high data rate to ultra-low power applications, and from G-b per second to RFID systems. One specific area, in particular, is in wireless data transmission for implantable bio-medical applications. To understand how brain functions, neural scientists are in pursuit of high-channel count, high-density recordings for freely moving animals; yet wire tethering issue has put the mission on pause. Wireless data transmission can address this tethering problem, but there are still many challenges to be conquered. In this work, an ultra-low power ultra-wide band (UWB) transmitter with feedforward pulse generation scheme is proposed to resolve the long-existing problem in UWB transmitter. It provides a high-data rate capability to enable 1000 channels in broadband neural recording, assuming 10-bit resolution with a sampling rate of 20 kHz to accommodate both action potential (AP) and local field potential (LFP) recording, while remaining in ultra- low power consumption at 4.32 pJ/b. For the bi-directional communication between the wireless and recording/ stimulating module, a bit-wise time-division (B-TDD) duplex transceiver without cancellation scheme is presented. The receiver works at U-NII band (5.2GHz) and shares the same antenna with UWB transmitter. This significantly reduces the area consumption as well as power consumption for implantable systems. The system can support uplink at 200 Mbps for 1000 recording channels and downlink at 10 Mbps for 36 stimulation channels. With a 3.7 Volt 25mAh rechargeable battery, the system should be able to operate more than 1.5 hours straight for both recording and stimulation, assuming 1 LED channel with 100 µA, 10% duty-cycled stimulating current. The B-TDD transceiver is integrated with a dedicated recording/ stimulation optogenetic IC chip to demonstrate as a complete wireless system for implantable broadband optogenetic neural modulation and recording. The fully integrated system is less than 5 gram, which is suitable for rodent experiments.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/155242/1/yujulin_1.pd