Design and Analysis of Low-power Millimeter-Wave SiGe BiCMOS Circuits with Application to Network Measurement Systems

Interest in millimeter (mm-) wave frequencies covering the spectrum of 30-300 GHz has been steadily increasing. Advantages such as larger absolute bandwidth and smaller form-factor have made this frequency region attractive for numerous applications, including high-speed wireless communication, sensing, material science, health, automotive radar, and space exploration. Continuous development of silicon-germanium heterojunction bipolar transistor (SiGe HBT) and associated BiCMOS technology has achieved transistors with fT/fmax of 505/720 GHz and integration with 55 nm CMOS. Such accomplishment and predictions of beyond THz performance have made SiGe BiCMOS technology the most competitive candidate for addressing the aforementioned applications. Especially for mobile applications, a critical demand for future mm-wave applications will be low DC power consumption (Pdc), which requires a substantial reduction of supply voltage and current. Conventionally, reducing the supply voltage will lead to HBTs operating close to or in the saturation region, which is typically avoided in mm-wave circuits due to expectated performance degradation and often inaccurate models. However, due to only moderate speed reduction at the forward-biased base-collector voltage (VBC) up to 0.5 V and the accuracy of the compact model HICUM/L2 also in saturation, low-power mm-wave circuits with SiGe HBTs operating in saturation offer intriguing benefits, which have been explored in this thesis based on 130 nm SiGe BiCMOS technologies: • Different low-power mm-wave circuit blocks are discussed in detail, including low-noise amplifiers (LNAs), down-conversion mixers, and various frequency multipliers covering a wide frequency range from V-band (50-75 GHz) to G-band (140-220 GHz). • Aiming at realizing a better trade-off between Pdc and RF performance, a drastic decrease in supply voltage is realized with forward-biased VBC, forcing transistors of the circuits to operate in saturation. • Discussions contain the theoretical analysis of the key figure of merits (FoMs), topology and bias selection, device sizing, and performance enhancement techniques. • A 173-207 GHz low-power amplifier with 23 dB gain and 3.2 mW Pdc, and a 72-108 GHz low-power tunable amplifier with 10-23 dB gain and 4-21 mW Pdc were designed. • A 97 GHz low-power down-conversion mixer was presented with 9.6 dB conversion gain (CG) and 12 mW Pdc. • For multipliers, a 56-66 GHz low-power frequency quadrupler with -3.6 dB peak CG and 12 mW Pdc, and a 172-201 GHz low-power frequency tripler with -4 dB peak CG and 10.5 mW Pdc were realized. By cascading these two circuits, also a 176-193 GHz low-power ×12 multiplier was designed, achieving -11 dBm output power with only 26 mW Pdc. • An integrated 190 GHz low-power receiver was designed as one receiving channel of a G-band frequency extender specifically for a VNA-based measurement system. Another goal of this receiver is to explore the lowest possible Pdc while keeping its highly competitive RF performance for general applications requiring a wide LO tuning range. Apart from the low-power design method of circuit blocks, the careful analysis and distribution of the receiver FoMs are also applied for further reduction of the overall Pdc. Along this line, this receiver achieved a peak CG of 49 dB with a 14 dB tunning range, consuming only 29 mW static Pdc for the core part and 171 mW overall Pdc, including the LO chain. • All designs presented in this thesis were fabricated and characterized on-wafer. Thanks to the accurate compact model HICUM/L2, first-pass access was achieved for all circuits, and simulation results show excellent agreement with measurements. • Compared with recently published work, most of the designs in this thesis show extremely low Pdc with highly competitive key FoMs regarding gain, bandwidth, and noise figure. • The observed excellent measurement-simulation agreement enables the sensitivity analysis of each design for obtaining a deeper insight into the impact of transistor-related physical effects on critical circuit performance parameters. Such studies provide meaningful feedback for process improvement and modeling development.:Table of Contents Kurzfassung . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iv Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii 1 Introduction 1 1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 List of symbols and acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 Technology 7 2.1 Fabrication Technologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1.1 SiGe HBT performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1.2 B11HFC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1.3 SG13G2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1.4 SG13D7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2 Commonly Used Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2.1 Grounded-sidewall-shielded microstrip line . . . . . . . . . . . . . . . . . . 12 2.2.2 Zero-impedance Transmission Line . . . . . . . . . . . . . . . . . . . . . . 15 2.2.3 Balun . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.2.3.1 Active Balun . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.2.3.2 Passive Balun . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.3 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3 Low-power Low-noise Amplifiers 25 3.1 173-207 GHz Ultra-low-power Amplifier . . . . . . . . . . . . . . . . . . . . . . . 25 3.1.1 Topology Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.1.2 Bias Dependency of the Small-signal Performance . . . . . . . . . . . . . 27 3.1.2.1 Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.1.2.2 Bias vs Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.1.2.3 Bias vs Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.1.2.4 Bias vs Stability . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.1.3 Bias selection and Device sizing . . . . . . . . . . . . . . . . . . . . . . . . 36 3.1.3.1 Bias Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.1.3.2 Device Sizing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.1.4 Performance Enhancement Technologies . . . . . . . . . . . . . . . . . . . 41 3.1.4.1 Gm-boosting Inductors . . . . . . . . . . . . . . . . . . . . . . . 41 3.1.4.2 Stability Enhancement . . . . . . . . . . . . . . . . . . . . . . . 43 3.1.4.3 Noise Improvement . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.1.5 Circuit Realization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.1.5.1 Layout Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.1.5.2 Inductors Design . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.1.5.3 Dual-band Matching Network . . . . . . . . . . . . . . . . . . . 48 3.1.5.4 Circuit Implementation . . . . . . . . . . . . . . . . . . . . . . . 50 3.1.6 Results and Discussions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.1.6.1 Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.1.6.2 Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . 51 3.1.6.3 Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 3.2 72-108 GHz Low-Power Tunable Amplifier . . . . . . . . . . . . . . . . . . . . . . 55 3.2.1 Configuration, Sizing, and Bias Tuning Range . . . . . . . . . . . . . . . . 55 3.2.2 Regional Matching Network . . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.2.2.1 Impedance Variation . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.2.2.2 Regional Matching Network Design . . . . . . . . . . . . . . . . 60 3.2.3 Circuit Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 3.2.4 Results and Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 3.2.4.1 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 3.2.4.2 Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 3.3 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 4 Low-power Down-conversion Mixers 73 4.1 97 GHz Low-power Down-conversion Mixer . . . . . . . . . . . . . . . . . . . . . 74 4.1.1 Mixer Design and Implementation . . . . . . . . . . . . . . . . . . . . . . 74 4.1.1.1 Mixer Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 4.1.1.2 Bias Selection and Device Sizing . . . . . . . . . . . . . . . . . . 77 4.1.1.3 Mixer Implementation . . . . . . . . . . . . . . . . . . . . . . . . 79 4.1.2 Results and Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 4.1.2.1 Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . 80 4.1.2.2 Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 4.2 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 5 Low-power Multipliers 87 5.1 General Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 5.2 56-66 GHz Low-power Frequency Quadrupler . . . . . . . . . . . . . . . . . . . . 89 5.3 172-201 GHz Low-power Frequency Tripler . . . . . . . . . . . . . . . . . . . . . 93 5.4 176-193 GHz Low-power ×12 Frequency Multiplier . . . . . . . . . . . . . . . . . 96 5.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 6 Low-power Receivers 101 6.1 Receiver Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 6.2 LO Chain (×12) Integrated 190 GHz Low-Power Receiver . . . . . . . . . . . . . 104 6.2.1 Receiver Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 6.2.2 Low-power Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 6.2.3 Building Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 6.2.3.1 LNA and LO DA . . . . . . . . . . . . . . . . . . . . . . . . . . 108 6.2.3.2 Tunable Mixer and IF BA . . . . . . . . . . . . . . . . . . . . . 111 6.2.3.3 65 GHz (V-band) Quadrupler . . . . . . . . . . . . . . . . . . . 116 6.2.3.4 G-band Tripler . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 6.2.4 Receiver Results and Discussion . . . . . . . . . . . . . . . . . . . . . . . 123 6.2.5 Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 6.2.6 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 6.3 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 7 Conclusions 133 7.1 Summaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 7.2 Outlook . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Bibliography 135 List of Figures 149 List of Tables 157 A Derivation of the Gm 159 A.1 Gm of standard cascode stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 A.2 Gm of cascode stage with Lcas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 A.3 Gm of cascode stage with Lb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 B Derivation of Yin in the stability analysis 163 C Derivation of Zin and Zout 165 C.1 Zin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 C.2 Zout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 D Derivation of the cascaded oP1dB 169 E Table of element values for the designed circuits 17

A SINGLE POWER SUPPLY 0.1-3.5 GHZ LOW NOISE AMPLIFIER DESIGN USING A LOW COST 0.5 µM D-MODE PHEMT PROCESS

Design and testing results of a single power supply wide-band low noise amplifier (LNA) based on low cost 0.5 µm D-mode pHEMT process are presented. It is shown that the designed cascode LNA has operating frequency range up to 3.5 GHz, power gain above 15 dB, noise figure below 2.2 dB, output linearity above 17 dBm and power consumption less than 325 mW. Potential immunity of the LNA to total ionizing dose and destructive single event effects exceed 300 krad and 60 MeV·cm2/mg respectively

Fully-Integrated Millimeter-Wave Duplexer Modules with Internal Power Amplifier and Low Noise Amplifier on 0.18-µm Bicmos Process For FDD 5g and Other Millimeter-Wave Applications

This research demonstrates two novel millimeter-wave (mm-wave) fully-integrated frequency-division duplexing (FDD) transmitting-receiving (TX-RX) front-end modules, including duplexer (DUX), power amplifier (PA), and low noise amplifier (LNA) on TowerJazz 0.18-µm SiGe BiCMOS. Additionally, two new proposed structures of BiCMOS PAs operating at mm-wave ranges are presented. These new contributions would benefit the developments of next generation wireless communications as well as other mm-wave wireless systems. First, for the proposed structures of BiCMOS PAs, we adopt both advantages of hetero-junction bipolar transistor (HBT) and metal-oxide-semiconductor field-effect transistor (MOSFET, NMOS) to improve PA performances such as larger maximum output power (Psat), higher gain, and better output 1-dB compression point (OP1dB). A detail investigation about cascode amplifiers of the HBT and NMOS combinations is presented. Ultimately, HBT with body-floating NMOS structure can provide medium gain with higher linear output power. The other new structure PA is three transistors stacked-amplifier, which is two stacked HBT and cascoded with a body-floating NMOS, leading to decent gain, larger Psat, and OP1dB. A SAW-less high-isolation fully-integrated 23.5–36.2-GHz FDD TX-RX front-end module, containing a DUX, PA, and differential LNA, is demonstrated on a single Si substrate to facilitate the development of system with DUX on a chip (SoC). The isolation between PA output and LNA input is better than 42 dB in 13 GHz bandwidth (BW). For the RX path, LNA has better than 19 dB gain with the minimum 13.8 dB noise figure (NF) at 28 GHz. On the TX path, PA provides about 12.9 dB gain with better than 12.5 dBm Psat in BW. TX signals leakage through Si-substrate is also considered and suppressed, using PA with deep-N-well structure and p-type/n-type grounding guard ring. This module only occupies 2.1-mm2 without dc and RF pads. In order to overcome the antenna imbalance issue of electrical balanced DUXs (EBDs) and high power consumption issue of active DUXs, a new power-efficient 28 GHz TXRX front-end module with more than 60-dB TX-RX isolation, including DUX, PA, and LNA, is designed, which combines the advantage of passive microwave circuit and active cancellation technique to achieve higher TX-RX isolation, low NF, and being power-efficient. The cancellation path consists of a variable gain amplifier (VGA) and reflection-type phase-shifter (RT-PS) to control the feedback signal amplitude and phase. A detailed analysis and design methodology are also proposed. This narrow-band TX-RX module also occupies small area with 2-mm2 without dc and RF pads

High dynamic range low noise amplifier and wideband hybrid phase shifter for SiGe BiCMOS phased array T/R modules

Transmit/Receive Module (T/R Module) is one of the most essential blocks for Phased Array Radio Detection and Ranging (RADAR) system; due to being very influential on system level performance. To achieve high performance specifications, T/R Module structures are constructed with using III-V devices, which has some significant disadvantages; they are costly, and also consume too much area and power. As a result, application area of T/R Module is mainly restricted with the military and dedicated applications. In recent years, SiGe BiCMOS technology has started to be an emerging competitor to III-V devices, with the help of bandgap engineering. SiGe BiCMOS based T/R Module structures are facilitating similar or better performance parameters with a much lower cost, which gives a chance to T/R Module not only used for military purposes, but also for commercial applications. For this reason, this thesis has focused on SiGe BiCMOS based X-Band T/R Module, specifically on its two significant blocks; Low Noise Amplifier (LNA), and Phase Shifter. Low Noise Amplifier is the first block of the receiver chain of the T/R Module; as a result its performance is very influential on the metrics of receiver, such as Noise Figure (NF), and gain. In this thesis, designing procedures for three different high dynamic range LNA structures are described, using 0.13μm SiGe IHP-Microelectronics and 0.13μm SiGe IBM technology. To achieve a high dynamic range, three different methodologies implemented and compared; single-stage cascode LNA, telescopic LNA, and two-stage cascode LNA. Among these, two-stage cascode LNA achieved better performance metrics of -3.72dBm level for input-compression point, total gain exceeding 20.5dB, a NF performance of about 2dB, and a power consumption of 115.8mW. Phase Shifter is used both in receiver and transmitting chain, as a result it is also crucial for the performance of the T/R Module. The design, implemented in 0.13μm SiGe IBM technology, had aimed to combine advantages of different topologies, such as passive phase shifter and vector modulator, to achieve a high phase resolution in wide bandwidth, and high linearity. The designed hybrid Phase Shifter achieves 6-Bit operation with 6.75GHz of bandwidth and 15dBm of input-P1dB. Moreover, design can be switched to 7-Bit phase shifter with 4.5GHz, without requiring any additional circuitry

SiGe BiCMOS active phase shifter design for W-band automotive radar applications

In this thesis, the design and measurement results of the fabricated LNA and phase shifter chips to be utilized in W-band Automotive Radar Applications are presented. The chips are manufactured using 0.13μm and 0.25μm SiGe HBT technologies. Observing the high insertion loss of the fabricated 4-bit MEMS based digital phase shifter which is around 15.3-18.1dB, two active phase shifter designs based on different vector-modulator topologies are offered. Amongst these structures, three-way active phase shifter is composed of Wilkinson power divider/combiner which separates the input signal into three vectors, additional phase lines dividing the 360o phase spectrum into three regions by adding 120o consecutive phase to each vector and LNAs to rotate the main antenna beam in these regions by the weighted sum of vectors. According to measurement results of the 100mW consuming 1.65mm2-sized chip, continuous 360o phase shifting is clearly achieved with 11dB peak gain at 77GHz, no insertion loss up to 90GHz and return losses better than 10dB for all the phase states. On the other hand, a two way I/Q type MEMS based active phase shifter is also in fabrication. The continuous phase shifting is realized in I- and Q-separated two amplification stages, using weighted sum method, to rotate in a single 90o quadrant and then employs 1-bit (0o-180o) MEMS phase shifter blocks to cover 360o in 4 states by shifting this quadrant about 90o. The simulation results of 3.74mm2 chip point out above-15dB input/output return loss and a variable 3-7.5dB gain at 77GHz with the tuned LNA voltages. Using these active phase shifters, phased array radars could provide higher gain in a smaller die area with reduced cost due to the used SiGe technology and automotive radars with high perfromances could be achieved

A SiGe BiCMOS LNA for mm-wave applications

A 5 GHz continuous unlicensed bandwidth is available at millimeter-wave (mm-wave) frequencies around 60 GHz and offers the prospect for multi gigabit wireless applications. The inherent atmospheric attenuation at 60 GHz due to oxygen absorption makes the frequency range ideal for short distance communication networks. For these mm-wave wireless networks, the low noise amplifier (LNA) is a critical subsystem determining the receiver performance i.e., the noise figure (NF) and receiver sensitivity. It however proves challenging to realise high performance mm-wave LNAs in a silicon (Si) complementary metal-oxide semiconductor (CMOS) technology. The mm-wave passive devices, specifically on-chip inductors, experience high propagation loss due to the conductivity of the Si substrate at mm-wave frequencies, degrading the performance of the LNA and subsequently the performance of the receiver architecture. The research is aimed at realising a high performance mm-wave LNA in a Si BiCMOS technology. The focal points are firstly, the fundamental understanding of the various forms of losses passive inductors experience and the techniques to address these issues, and secondly, whether the performance of mm-wave passive inductors can be improved by means of geometry optimising. An associated hypothesis is formulated, where the research outcome results in a preferred passive inductor and formulates an optimised passive inductor for mm-wave applications. The performance of the mm-wave inductor is evaluated using the quality factor (Q-factor) as a figure of merit. An increased inductor Q-factor translates to improved LNA input and output matching performance and contributes to the lowering of the LNA NF. The passive inductors are designed and simulated in a 2.5D electromagnetic (EM) simulator. The electrical characteristics of the passive structures are exported to a SPICE netlist which is included in a circuit simulator to evaluate and investigate the LNA performance. Two LNAs are designed and prototyped using the 13μ-m SiGe BiCMOS process from IBM as part of the experimental process to validate the hypothesis. One LNA implements the preferred inductor structures as a benchmark, while the second LNA, identical to the first, replaces one inductor with the optimised inductor. Experimental verification allows complete characterization of the passive inductors and the performance of the LNAs to prove the hypothesis. According to the author's knowledge, the slow-wave coplanar waveguide (S-CPW) achieves a higher Q-factor than microstrip and coplanar waveguide (CPW) transmission lines at mm-wave frequencies implemented for the 130 nm SiGe BiCMOS technology node. In literature, specific S-CPW transmission line geometry parameters have previously been investigated, but this work optimises the signal-to-ground spacing of the S-CPW transmission lines without changing the characteristic impedance of the lines. Optimising the S-CPW transmission line for 60 GHz increases the Q-factor from 38 to 50 in simulation, a 32 % improvement, and from 8 to 10 in measurements. Furthermore, replacing only one inductor in the output matching network of the LNA with the higher Q-factor inductor, improves the input and output matching performance of the LNA, resulting in a 5 dB input and output reflection coefficient improvement. Although a 5 dB improvement in matching performance is obtained, the resultant noise and gain performance show no significant improvement. The single stage LNAs achieve a simulated gain and NF of 13 dB and 5.3 dB respectively, and dissipate 6 mW from the 1.5 V supply. The LNA focused to attain high gain and a low NF, trading off linearity and as a result obtained poor 1 dB compression of -21.7 dBm. The LNA results are not state of the art but are comparable to SiGe BiCMOS LNAs presented in literature, achieving similar gain, NF and power dissipation figures.Dissertation (MEng)--University of Pretoria, 2012.Electrical, Electronic and Computer Engineeringunrestricte

Millimeter-Wave Concurrent Dual-Band BiCMOS RFICs for Radar and Communication RF Front-End

The recent advancement in silicon-based technologies has offered the opportunity for the development of highly-integrated circuits and systems in the millimeter-wave frequency regime. In particular, the demand for high performance multi-band multi-mode radar and communication systems built on silicon-based technologies has been increased dramatically for both military and commercial applications. This dissertation presents the design and implementation of advanced millimeter-wave front-end circuits in SiGe BiCMOS process including a transmit/receive switch module with integrated calibration function, low noise amplifier, and power amplifier for millimeter-wave concurrent dual-band dual-polarization radars and communication systems. The proposed circuits designed for the concurrent dual-band dual-polarization radars and communication systems were fabricated using 0.18-μm BiCMOS process resulting in novel circuit architectures for concurrent multi-band operation. The developed concurrent dual-band circuits fabricated on 0.18-μm BiCMOS process include the T/R/Calibration switch module for digital beam forming array system at 24.5/35 GHz, concurrent dual-band low noise amplifiers at 44/60 GHz, and concurrent dual-band power amplifier at 44/60 GHz. With having all the design frequencies closely spaced to each other showing the frequency ratio below 1.43, the designed circuits provided the integrated dual-band filtering function with Q-enhanced frequency responses. Inspired by the composite right/left- handed metamaterial transmission line approaches, the integrated Q-enhanced filtering sub-circuits provided unprecedented dual-band filtering capability. The new concurrent dual-band dual-mode circuits and system architecture can provide enhanced radar and communication system performance with extended coverage, better image synthesis and target locating by the enhanced diversity. The circuit level hardware research conducted in this dissertation is expected to contribute to enhance the performance of multi-band multi-mode imaging, sensing, and communication array systems

ANALYSIS AND DESIGN OF SILICON-BASED MILLIMETER-WAVE AMPLIFIERS

Ph.DDOCTOR OF PHILOSOPH