Capacitance-to-Digital Converter for Operation Under Uncertain Harvested Voltage down to 0.3V with No Trimming, Reference and Voltage Regulation

In Paper 5.2, the National University of Singapore and Politecnico di Torino present a capacitance-to-digital converter (CDC) for direct harvester-powered low-cost systems, showing a 7-bit ENOB down to 0.3V at 1.37nW power without any external reference or voltage-regulation requirements

A Temperature – and Supply- Variation Robust 2nd-Order Sigma-Delta Modulation for Capacitive Sensing

Capacitance to digital converter, VCO quantizer, Sigma-Delta modulation, Supply variation, temperature variationIn this paper, I proposed a temperature- and supply variation robust 2nd-order sigma-delta modulation circuit for capacitive sensing. Capacitive sensing by conventional circuits is basically supply sensitive. Capacitance is sensed by reading the charge that is equal to the difference between the capacitance value of the capacitor and the capacitor to be sensed. In this method, the amount of charge is dependent on the supply, so it is insensitive to supply variation. In this paper, the capacitance is read by using the time determined by the discharge characteristics when a capacitor called T0V meets the resistance component. The charge accumulated in the capacitor is certainly influenced by the supply value, but capacitive sensing is performed using the characteristic that the time taken to discharge the charge to zero is always constant. In the process, VCO (Voltage-Controlled-Oscillator) based ADC (Analog-to-Digital Converter) was used to increase the resolution by utilizing the noise shaping effect of sigma-delta ADC. In the process, the resistor is switched to a switched capacitor to obtain robust characteristics against temperature variations. Unlike resistance whose values change with temperature, capacitance are relatively robust to temperature effects. By using the characteristics, a circuit having robust characteristics in temperature variation as well as robust in supply variation.openAbstract i List of contents iii List of figures iv List of figures v Ⅰ. Introduction 1.1 Motivation and Objective 1 1.2 Theses outline 3 ⅠI. Supply- Variation Robust 2nd-Order Sigma-Delta Modulation 2.1 Supply Independent Technique 4 2.2 Injection Locking Current Controlled Oscillator 8 2.3 VCO Based ADC 13 2.4 Full Architecture 16 2.4.1 Control Block 19 2.4.2 Block Diagram 21 2.5 Schematic and Layout 23 III. Temperature- and Supply- Variation Robust 2nd-Order Sigma-Delta Modulation 3.1 Switched Capacitor DAC 31 3.2 Switched Capacitor Clock Generator 36 3.3 Control Block 38 3.4 Schematic 39 IV. Simulation and Measurement Result 4.1 Resistor DAC Circuit 42 4.1.1 Measurement Result 42 4.2 Switched Capacitor DAC Circuit 45 4.2.1 Simulation Result 45 V. Conclusion본 논문은 전원변화 및 온도변화에도 안정적으로 정전용량을 읽어낼 수 있는 2차 시그마-델타 변조기 회로이다. 커패시터의 방전 시간이 전원의 영향이 아닌 정전용량과 저항 값에만 영향을 받는다는 점을 이용하여 회로를 구성하였다. 또한 저항이 온도변화에 따라서 일정한 값을 유지하기 힘들다는 점을 보완하기위해 switched capacitor 기법을 사용하였다. 커패시터는 저항에 비해 상대적으로 온도변화에도 정전용량을 안정적인 값으로 유지할 수 있다. 이 점을 이용하여 전원변화뿐 만이 아닌 온도변화에도 강인한 특성을 가질 수 있게 된다. 또 전압제어발진기를 활용한 아날로그-디지털 변환기법도 사용되었다. 전압제어발진기에 ‘전압제어발진기 기반 양자화기’라는 양자화를 할 수 있는 회로를 연결하여 동작이 진행된다. 이 기법을 사용하게 되면 양자화오류의 성분들이 백색잡음처럼 모든 주파수대역에 걸쳐서 골고루 존재하는 것이 아닌, 고주파 쪽을 향해 20dB의 기울기를 가지며 상승하는 형태로 나타난다. 최종적인 전체 루프의 특성을 확인하면 40dB의 기울기를 가지며 상승하는 형태를 갖는다. 이 특성을 통하여 동작 대역폭이 아닌 더 고주파 영역으로 양자화 오류 성분들을 밀어낼 수 있다는 장점이 있다. 그 결과, SNR이 상승하게 되어 최종적으로 정전용량을 읽어낼 수 있는 분해능 성능이 좋아지게 된다.MasterdCollectio

A Review Of Implementing Adc In Rfid Sensor

Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)The general considerations to design a sensor interface for passive RFID tags are discussed. This way, power and timing constraints imposed by ISO/IEC 15693 and ISO/IEC 14443 standards to HF RFID tags are explored. A generic multisensor interface is proposed and a survey analysis on the most suitable analog-to-digital converters for passive RFID sensing applications is reported. The most appropriate converter type and architecture are suggested. At the end, a specific sensor interface for carbon nanotube gas sensors is proposed and a brief discussion about its implemented circuits and preliminary results is made.Region Rhone-Alpes (France)CNPq (Brazil)INCT/NAMITEC (Brazil)Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq

A Review of Implementing ADC in RFID Sensor

The general considerations to design a sensor interface for passive RFID tags are discussed. This way, power and timing constraints imposed by ISO/IEC 15693 and ISO/IEC 14443 standards to HF RFID tags are explored. A generic multisensor interface is proposed and a survey analysis on the most suitable analog-to-digital converters for passive RFID sensing applications is reported. The most appropriate converter type and architecture are suggested. At the end, a specific sensor interface for carbon nanotube gas sensors is proposed and a brief discussion about its implemented circuits and preliminary results is made

A Review Of Implementing Adc In Rfid Sensor

Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)The general considerations to design a sensor interface for passive RFID tags are discussed. This way, power and timing constraints imposed by ISO/IEC 15693 and ISO/IEC 14443 standards to HF RFID tags are explored. A generic multisensor interface is proposed and a survey analysis on the most suitable analog-to-digital converters for passive RFID sensing applications is reported. The most appropriate converter type and architecture are suggested. At the end, a specific sensor interface for carbon nanotube gas sensors is proposed and a brief discussion about its implemented circuits and preliminary results is made.Region Rhone-Alpes (France)CNPq (Brazil)INCT/NAMITEC (Brazil)Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq

Energy-efficient data converter design in scaled CMOS technology

Data converters bridge the physical and digital worlds. They have been the crucial building blocks in modern electronic systems, and are expected to have a growing significance in the booming era of Internet-of-Things (IoT) and 5G communications. The applications raise energy-efficiency requirements for both low-speed and high-speed converters since they are widely deployed in wireless sensor nodes and portable devices. To explore the solutions, the author worked on three directions: 1) techniques to improve the efficiency of the low-speed converters including the comparator; 2) techniques to develop high-speed data converters including the reference stabilization; 3) new architecture to improve the efficiency of the capacitance-to-digital converter (CDC). In the first part, a power-efficient 10-bit SAR ADC featured with a gain-boosted dynamic comparator is presented. In energy-constrained applications, the converter is usually supplied with low supply voltage (e.g., 0.3 V-0.5 V), which reduces the comparator pre-amplifier (pre-amp) gain and results in higher noise. A novel comparator topology with a dynamic common-gate stage is proposed to increase the pre-amplification gain, thereby reducing noise and offset. Besides, statistical estimation and loading switching techniques are combined to further improve energy efficiency. A 40-nm CMOS prototype achieves a Walden FoM of 1.5 fJ/conversion-step while operating at 100-kS/s from a 0.5-V supply. To further improve the energy-efficiency of the comparator, a novel dynamic pre-amp is proposed. By using an inverter-based input pair powered by a floating reservoir capacitor, the pre-amp realizes both current reuse and dynamic bias, thereby significantly boosting g [subscript m] /I [subscript D] and reducing noise. Moreover, it greatly reduces the influence of the input common-mode (CM) voltage on the comparator performance, including noise, offset, and delay. A prototype comparator in 180-nm achieves 46-μV input-referred noise while consuming only 1 pJ per comparison under 1.2-V supply, which represents greater than 7 times energy efficiency boost compared to that of a Strong-Arm (SA) latch. The second part of this dissertation focuses on high-speed data converter techniques. A 10-bit high-speed two-stage loop-unrolled SAR ADC is presented. To reduce the SAR logic delay and power, each bit uses a dedicated comparator to store its output and generate an asynchronous clock for the next comparison. To suppress the comparator offset mismatch induced non-linearity, a shared pre-amp are employed in the second fine stage, which is implemented by a dynamic latch to avoid static power consumption. The prototype ADC in 40-nm CMOS achieves 55-dB peak SNDR at 200-MS/s sampling rate without any calibration. A key limiting factor for the SAR ADC to simultaneously achieve high speed and high resolution is the reference ripple settling problem caused by DAC switching. Unlike prior techniques that aim to minimize the reference ripple which requires large reference buffer power or on-chip decoupling capacitance area, this work proposes a new perspective: it provides an extra path for the full-sized reference ripple to couple to the comparator but with an opposite polarity, so that the effect of the reference ripple is canceled out, thus ensuring an accurate conversion result. The prototype 10-bit 120-MS/s SAR ADC is fabricated in 40-nm CMOS process and achieves an SNDR of 55 dB with only 3 pF reference decoupling capacitor. Finally, this dissertation also presents the design of an incremental time-domain two-step CDC. Unlike the classic two-step CDC, this work replaces the OTA-based active-RC integrator with a VCO-based integrator and performs time domain (TD) ΔΣ modulation. The VCO is mostly digital and consumes low power. Featuring the infinite DC gain in phase domain and intrinsic spatial phase quantization, this TDΔΣ enables a CDC design, achieving 85-dB SQNR by having only a 4-bit quantizer, a 1st-order loop and a low OSR of 15. The prototype fabricated in 40-nm CMOS achieves a resolution of 0.29 fF while dissipating only 0.083 nJ per conversion, which improves the energy efficiency by greater than 2 times comparing to that of state-of-the-art CDCsElectrical and Computer Engineerin

Data Conversion Within Energy Constrained Environments

Within scientific research, engineering, and consumer electronics, there is a multitude of new discrete sensor-interfaced devices. Maintaining high accuracy in signal quantization while staying within the strict power-budget of these devices is a very challenging problem. Traditional paths to solving this problem include researching more energy-efficient digital topologies as well as digital scaling.;This work offers an alternative path to lower-energy expenditure in the quantization stage --- content-dependent sampling of a signal. Instead of sampling at a constant rate, this work explores techniques which allow sampling based upon features of the signal itself through the use of application-dependent analog processing. This work presents an asynchronous sampling paradigm, based off the use of floating-gate-enabled analog circuitry. The basis of this work is developed through the mathematical models necessary for asynchronous sampling, as well the SPICE-compatible models necessary for simulating floating-gate enabled analog circuitry. These base techniques and circuitry are then extended to systems and applications utilizing novel analog-to-digital converter topologies capable of leveraging the non-constant sampling rates for significant sample and power savings

DESIGN OF LOW-POWER LOW-VOLTAGE SUCCESSIVE-APPROXIMATION ANALOG-TO-DIGITAL CONVERTERS

Ph.DDOCTOR OF PHILOSOPH

A Low-Power, Reconfigurable, Pipelined ADC with Automatic Adaptation for Implantable Bioimpedance Applications

Biomedical monitoring systems that observe various physiological parameters or electrochemical reactions typically cannot expect signals with fixed amplitude or frequency as signal properties can vary greatly even among similar biosignals. Furthermore, advancements in biomedical research have resulted in more elaborate biosignal monitoring schemes which allow the continuous acquisition of important patient information. Conventional ADCs with a fixed resolution and sampling rate are not able to adapt to signals with a wide range of variation. As a result, reconfigurable analog-to-digital converters (ADC) have become increasingly more attractive for implantable biosensor systems. These converters are able to change their operable resolution, sampling rate, or both in order convert changing signals with increased power efficiency. Traditionally, biomedical sensing applications were limited to low frequencies. Therefore, much of the research on ADCs for biomedical applications focused on minimizing power consumption with smaller bias currents resulting in low sampling rates. However, recently bioimpedance monitoring has become more popular because of its healthcare possibilities. Bioimpedance monitoring involves injecting an AC current into a biosample and measuring the corresponding voltage drop. The frequency of the injected current greatly affects the amplitude and phase of the voltage drop as biological tissue is comprised of resistive and capacitive elements. For this reason, a full spectrum of measurements from 100 Hz to 10-100 MHz is required to gain a full understanding of the impedance. For this type of implantable biomedical application, the typical low power, low sampling rate analog-to-digital converter is insufficient. A different optimization of power and performance must be achieved. Since SAR ADC power consumption scales heavily with sampling rate, the converters that sample fast enough to be attractive for bioimpedance monitoring do not have a figure-of-merit that is comparable to the slower converters. Therefore, an auto-adapting, reconfigurable pipelined analog-to-digital converter is proposed. The converter can operate with either 8 or 10 bits of resolution and with a sampling rate of 0.1 or 20 MS/s. Additionally, the resolution and sampling rate are automatically determined by the converter itself based on the input signal. This way, power efficiency is increased for input signals of varying frequency and amplitude