127 research outputs found
Theory and applications of delta-sigma analogue-to-digital converters without negative feedback
Analog-to-digital converters play a crucial role in modern audio and communication design. Conventional Nyquist converters are suitable only for medium resolutions and require analog components that are precise and highly immune to noise and interference. In contrast, oversampling converters can achieve high resolutions (>20bits) and can be implemented using straightforward, high-tolerance analog components. In conventional oversampled modulators, negative feedback is applied in order to control the dynamic behavior of a system and to realize the attenuation of the quantization noise in the signal band due to noise shaping. However, feedback can also introduce undesirable effects such as limit cycles, jitter problems in continuous-time topologies, and infinite impulse responses. Additionally, it increases the system complexity due to extra circuit components such as nonlinear multi-bit digital-to-analog converters in the feedback path. Moreover, in certain applications such as wireless, biomedical sensory, or microphone implementations feedback cannot be applied. As a result, the main goal of this thesis is to develop sigma-delta data converters without feedback. Various new delta-sigma analog-to-digital converter topologies are explored their mathematical models are presented. Simulations are carried out to validate these models and to show performance results. Specifically, two topologies, a first-order and a second-order oscillator-based delta-sigma modulator without feedback are described in detail. They both can be implemented utilizing VCOs and standard digital gates, thus requiring only few components. As proof of concept, two digital microphones based on these delta-sigma converters without feedback were implemented and experimental results are given. These results show adequate performance and provide a new approach of measuring
VCO-based ADCs Design Techniques for Communication Systems
This work presents a novel technique to implement voltage-controlled oscillator based continuous-time Delta-Sigma analog-to-digital converters (VCO-based CT-ΔΣ ADCs) in closed-loop configuration. Over the past years there has been an upward trend in the use of these type of converters for instrumentation, audio and communication applications. The reason is that they are mostly digital and thus benefit from advances in deep-submicron
CMOS processes. VCO-based ADCs have been widely studied in a great deal of papers and it is known that one of its main drawbacks is the non-linearity it presents. To overcome this issue, to place the VCO within a closed-loop is usually done to attenuate its input magnitude level. However, to do so it is needed a digital-to-analog converter (DAC) as in a conventional CT-ΔΣ, therefore it is required for the DAC to be simple and it cannot present a high number of elements, being the latter a bottleneck for implementing VCOs with a high
number of inverters. This works presents a technique that enables to use VCOs with
severals inverters while keeping the same number of DAC elements as before. Based upon previous theoretical studies of the VCO-based ADCs which model it as a pulse frequency modulation encoder, this new technique is analyzed and linear models are developed in order to study its viability at system level. Moreover, how impairments related to a real implementation affect the use of this technique are also analyzed.
The contributions proposed in this document are focused but not limited to communication applications.Máster Universitario en Ingeniería de Sistemas Electrónicos y Aplicaciones. Curso 2018/201
Linearization of Time-encoded ADCs Architectures for Smart MEMS Sensors in Low Power CMOS Technology
Mención Internacional en el título de doctorIn the last few years, the development of mobile technologies and machine learning
applications has increased the demand of MEMS-based digital microphones.
Mobile devices have several microphones enabling noise canceling, acoustic beamforming
and speech recognition. With the development of machine learning applications
the interest to integrate sensors with neural networks has increased.
This has driven the interest to develop digital microphones in nanometer CMOS
nodes where the microphone analog-front end and digital processing, potentially
including neural networks, is integrated on the same chip.
Traditionally, analog-to-digital converters (ADCs) in digital microphones have
been implemented using high order Sigma-Delta modulators. The most common
technique to implement these high order Sigma-Selta modulators is switchedcapacitor
CMOS circuits. Recently, to reduce power consumption and make them
more suitable for tasks that require always-on operation, such as keyword recognition,
switched-capacitor circuits have been improved using inverter-based operational
amplifier integrators. Alternatively, switched-capacitor based Sigma-
Delta modulators have been replaced by continuous time Sigma-Delta converters.
Nevertheless, in both implementations the input signal is voltage encoded
across the modulator, making the integration in smaller CMOS nodes more challenging
due to the reduced voltage supply.
An alternative technique consists on encoding the input signal on time (or
frequency) instead of voltage. This is what time-encoded converters do. Lately,
time-encoding converters have gained popularity as they are more suitable to
nanometer CMOS nodes than Sigma-Delta converters. Among the ones that have
drawn more interest we find voltage-controlled oscillator based ADCs (VCOADCs).
VCO-ADCs can be implemented using CMOS inverter based ring oscillators
(RO) and digital circuitry. They also show noise-shaping properties.
This makes them a very interesting alternative for implementation of ADCs in
nanometer CMOS nodes. Nevertheless, two main circuit impairments are present
in VCO-ADCs, and both come from the oscillator non-idealities. The first of them
is the oscillator phase noise, that reduces the resolution of the ADC. The second
is the non-linear tuning curve of the oscillator, that results in harmonic distortion
at medium to high input amplitudes.
In this thesis we analyze the use of time encoding ADCs for MEMS microphones
with special focus on ring oscillator based ADCs (RO-ADCs). Firstly, we
study the use of a dual-slope based SAR noise shaped quantizer (SAR-NSQ) in
sigma-delta loops. This quantizer adds and extra level of noise-shaping to the modulator, improving the resolution. The quantizer is explained, and equations
for the noise transfer function (NTF) of a third order sigma-delta using a second
order filter and the NSQ are presented.
Secondly, we move our attention to the topic of RO-ADCs. We present a high
dynamic range MEMS microphone 130nm CMOS chip based on an open-loop
VCO-ADC. This dissertation shows the implementation of the analog front-end
that includes the oscillator and the MEMS interface, with a focus on achieving
low power consumption with low noise and a high dynamic range. The digital
circuitry is left to be explained by the coauthor of the chip in his dissertation. The
chip achieves a 80dBA peak SNDR and 108dB dynamic range with a THD of 1.5%
at 128 dBSPL with a power consumption of 438μW.
After that, we analyze the use of a frequency-dependent-resistor (FDR) to implement
an unsampled feedback loop around the oscillator. The objective is to reduce
distortion. Additionally phase noise mitigation is achieved. A first topology
including an operational amplifier to increase the loop gain is analyzed. The design
is silicon proven in a 130 nm CMOS chip that achieves a 84 dBA peak SNDR
with an analog power consumption of 600μW. A second topology without the
operational amplifier is also analyzed. Two chips are designed with this topology.
The first chip in 130 nm CMOS is a full VCO-ADC including the frequencyto-
digital converter (F2D). This chip achieves a peak SNDR of 76.6 dBA with a
power consumption of 482μW. The second chip includes only the oscillator and
is implemented in 55nm CMOS. The peak SNDR is 78.15 dBA and the analog
power consumption is 153μW.
To finish this thesis, two circuits that use an FDR with a ring oscillator are
presented. The first is a capacity-to-digital converter (CDC). The second is a filter
made with an FDR and an oscillator intended for voice activity detection tasks
(VAD).En los últimos años, el desarrollo de las tecnologías móviles y las aplicaciones de
machine-learning han aumentado la demanda de micrófonos digitales basados
en MEMS. Los dipositivos móviles tienen varios micrófonos que permiten la cancelación
de ruido, el beamforming o conformación de haces y el reconocimiento
de voz. Con el desarrollo de aplicaciones de aprendizaje automático, el interés
por integrar sensores con redes neuronales ha aumentado. Esto ha impulsado el
interés por desarrollar micrófonos digitales en nodos CMOS nanométricos donde
el front-end analógico y el procesamiento digital del micrófono, que puede
incluir redes neuronales, está integrado en el mismo chip.
Tradicionalmente, los convertidores analógicos-digitales (ADC) en micrófonos
digitales han sido implementados utilizando moduladores Sigma-Delta de
orden elevado. La técnica más común para implementar estos moduladores Sigma-
Delta es el uso de circuitos CMOS de capacidades conmutadas. Recientemente,
para reducir el consumo de potencia y hacerlos más adecuados para las tareas que
requieren una operación continua, como el reconocimiento de palabras clave, los
convertidores Sigma-Delta de capacidades conmutadas has sido mejorados con
el uso de integradores implementados con amplificadores operacionales basados
en inversores CMOS. Alternativamente, los Sigma-Delta de capacidades conmutadas
han sido reemplazados por moduladores en tiempo continuo. No obstante,
en ambas implementaciones, la señal de entrada es codificada en voltaje durante
el proceso de conversión, lo que hace que la integración en nodos CMOS más
pequeños sea complicada debido a la menor tensión de alimentación.
Una técnica alternativa consiste en codificar la señal de entrada en tiempo (o
frecuencia) en lugar de tensión. Esto es lo que hacen los convertidores de codificación
temporal. Recientemente, los convertidores de codificación temporal
han ganado popularidad ya que son más adecuados para nodos CMOS nanométricos
que los convertidores Sigma-Delta. Entre los que más interés han despertado
encontramos los ADCs basados en osciladores controlados por tensión
(VCO-ADC). Los VCO-ADC se pueden implementar usando osciladores en anillo
(RO) implementados con inversores CMOS y circuitos digitales. Esta familia
de convertidores también tiene conformado de ruido. Esto los convierte en una
alternativa muy interesante para la implementación de convertidores en nodos
CMOS nanométricos. Sin embargo, dos problemas principales están presentes en
este tipo de ADCs debidos ambos a las no idealidades del oscilador. El primero
de los problemas es la presencia de ruido de fase en el oscilador, lo que reduce la resolución del ADC. El segundo es la curva de conversion voltaje-frecuencia no
lineal del oscilador, lo que causa distorsión a amplitudes medias y altas.
En esta tesis analizamos el uso de ADCs de codificación temporal para micrófonos
MEMS, con especial interés en ADCS basados en osciladores de anillo
(RO-ADC). En primer lugar, estudiamos el uso de un cuantificador SAR con conformado
de ruido (SAR-NSQ) en moduladores Sigma-Delta. Este cuantificador
agrega un orden adicional de conformado de ruido al modulador, mejorando la
resolución. En este documento se explica el cuantificador y obtienen las ecuaciones
para la función de transferencia de ruido (NTF) de un sigma-delta de tercer
orden usando un filtro de segundo orden y el NSQ.
En segundo lugar, dirigimos nuestra atención al tema de los RO-ADC. Presentamos
el chip de un micrófono MEMS de alto rango dinámico en CMOS de
130 nm basado en un VCO-ADC de bucle abierto. En esta tesis se explica la implementación
del front-end analógico que incluye el oscilador y la interfaz con
el MEMS. Esta implementación se ha llevado a cabo con el objetivo de lograr un
bajo consumo de potencia, un bajo nivel de ruido y un alto rango dinámico. La
descripción del back-end digital se deja para la tesis del couator del chip. La
SNDR de pico del chip es de 80dBA y el rango dinámico de 108dB con una THD
de 1,5% a 128 dBSPL y un consumo de potencia de 438μW.
Finalmente, se analiza el uso de una resistencia dependiente de frecuencia
(FDR) para implementar un bucle de realimentación no muestreado alrededor
del oscilador. El objetivo es reducir la distorsión. Además, también se logra la
mitigación del ruido de fase del oscilador. Se analyza una primera topologia de
realimentación incluyendo un amplificador operacional para incrementar la ganancia
de bucle. Este diseño se prueba en silicio en un chip CMOS de 130nm que
logra un pico de SNDR de 84 dBA con un consumo de potencia de 600μW en la
parte analógica. Seguidamente, se analiza una segunda topología sin el amplificador
operacional. Se fabrican y miden dos chips diseñados con esta topologia.
El primero de ellos en CMOS de 130 nm es un VCO-ADC completo que incluye
el convertidor de frecuencia a digital (F2D). Este chip alcanza un pico SNDR de
76,6 dBA con un consumo de potencia de 482μW. El segundo incluye solo el oscilador
y está implementado en CMOS de 55nm. El pico SNDR es 78.15 dBA y el
el consumo de potencia analógica es de 153μW.
Para cerrar esta tesis, se presentan dos circuitos que usan la FDR con un oscilador
en anillo. El primero es un convertidor de capacidad a digital (CDC). El
segundo es un filtro realizado con una FDR y un oscilador, enfocado a tareas de
detección de voz (VAD).Programa de Doctorado en Ingeniería Eléctrica, Electrónica y Automática por la Universidad Carlos III de MadridPresidente: Antonio Jesús Torralba Silgado.- Secretaria: María Luisa López Vallejo.- Vocal: Pieter Rombout
Data acquisition techniques based on frequency-encoding applied to capacitive MEMS microphones
Mención Internacional en el título de doctorThis thesis focuses on the development of capacitive sensor readout circuits
and data converters based on frequency-encoding. This research
has been motivated by the needs of consumer electronics industry, which
constantly demands more compact readout circuit for MEMS microphones
and other sensors. Nowadays, data acquisition is mainly based
on encoding signals in voltage or current domains, which is becoming
more challenging in modern deep submicron CMOS technologies.
Frequency-encoding is an emerging signal processing technique based
on encoding signals in the frequency domain. The key advantage of
this approach is that systems can be implemented using mostly-digital
circuitry, which benefits from CMOS technology scaling. Frequencyencoding
can be used to build phase referenced integrators, which can
replace classical integrators (such as switched-capacitor based integrators)
in the implementation of efficient analog-to-digital converters and
sensor interfaces. The core of the phase referenced integrators studied in
this thesis consists of the combination of different oscillator topologies
with counters and highly-digital circuitry.
This work addresses two related problems: the development of capacitive
MEMS sensor readout circuits based on frequency-encoding, and the
design and implementation of compact oscillator-based data converters
for audio applications.
In the first problem, the target is the integration of the MEMS sensor
into an oscillator circuit, making the oscillation frequency dependent on
the sensor capacitance. This way, the sound can be digitized by measuring
the oscillation frequency, using digital circuitry. However, a MEMS
microphone is a complex structure on which several parasitic effects can
influence the operation of the oscillator. This work presents a feasibility
analysis of the integration of a MEMS microphone into different oscillator
topologies. The conclusion of this study is that the parasitics of the
MEMS limit the performance of the microphone, making it inefficient.
In contrast, replacing conventional ADCs with frequency-encoding based
ADCs has proven a very efficient solution, which motivates the next
problem.
In the second problem, the focus is on the development of high-order
oscillator-based Sigma-Delta modulators. Firstly, the equivalence between classical
integrators and phase referenced integrators has been studied, followed
by an overview of state-of-art oscillator-based converters. Then,
a procedure to replace classical integrators by phase referenced integrators
is presented, including a design example of a second-order oscillator based
Sigma-Delta modulator. Subsequently, the main circuit impairments that
limit the performance of this kind of implementations, such as phase
noise, jitter or metastability, are described.
This thesis also presents a methodology to evaluate the impact of
phase noise and distortion in oscillator-based systems. The proposed
method is based on periodic steady-state analysis, which allows the rapid
estimation of the system dynamic range without resorting to transient
simulations. In addition, a novel technique to analyze the impact of
clock jitter in Sigma-Delta modulators is described.
Two integrated circuits have been implemented in 0.13 μm CMOS
technology to demonstrate the feasibility of high-order oscillator-based Sigma-Delta modulators. Both chips have been designed to feature secondorder
noise shaping using only oscillators and digital circuitry. The first
testchip shows a malfunction in the digital circuitry due to the complexity
of the multi-bit counters. The second chip, implemented using
single-bit counters for simplicity, shows second-order noise shaping and
reaches 103 dB-A of dynamic range in the audio bandwidth, occupying
only 0.04 mm2.Esta tesis se centra en el desarrollo de conversores de datos e interfaces
para sensores capacitivos basados en codificación en frecuencia. Esta
investigación está motivada por las necesidades de la industria, que constantemente
demanda reducir el tamaño de este tipo de circuitos. Hoy en
día, la adquisición de datos está basada principalmente en la codificación
de señales en tensión o en corriente. Sin embargo, la implementación
de este tipo de soluciones en tecnologías CMOS nanométricas presenta
varias dificultades.
La codificación de frecuencia es una técnica emergente en el procesado
de señales basada en codificar señales en el dominio de la frecuencia.
La principal ventaja de esta alternativa es que los sistemas pueden implementarse
usando circuitos mayoritariamente digitales, los cuales se
benefician de los avances de la tecnología CMOS. La codificación en
frecuencia puede emplearse para construir integradores referidos a la
fase, que pueden reemplazar a los integradores clásicos (como los basados
en capacidades conmutadas) en la implementación de conversores
analógico-digital e interfaces de sensores. Los integradores referidos a la
fase estudiados en esta tesis consisten en la combinación de diferentes
topologías de osciladores con contadores y circuitos principalmente digitales.
Este trabajo aborda dos cuestiones relacionadas: el desarrollo de circuitos
de lectura para sensores MEMS capacitivos basados en codificación
temporal, y el diseño e implementación de conversores de datos
compactos para aplicaciones de audio basados en osciladores.
En el primer caso, el objetivo es la integración de un sensor MEMS
en un oscilador, haciendo que la frecuencia de oscilación depe capacidad del sensor. De esta forma, el sonido puede ser digitalizado
midiendo la frecuencia de oscilación, lo cual puede realizarse usando circuitos
en su mayor parte digitales. Sin embargo, un micrófono MEMS es
una estructura compleja en la que múltiples efectos parasíticos pueden
alterar el correcto funcionamiento del oscilador. Este trabajo presenta
un análisis de la viabilidad de integrar un micrófono MEMS en diferentes
topologías de oscilador. La conclusión de este estudio es que los parasíticos
del MEMS limitan el rendimiento del micrófono, causando que esta
solución no sea eficiente. En cambio, la implementación de conversores
analógico-digitales basados en codificación en frecuencia ha demostrado
ser una alternativa muy eficiente, lo cual motiva el estudio del siguiente
problema.
La segunda cuestión está centrada en el desarrollo de moduladores Sigma-Delta de alto orden basados en osciladores. En primer lugar se ha estudiado
la equivalencia entre los integradores clásicos y los integradores
referidos a la fase, seguido de una descripción de los conversores basados
en osciladores publicados en los últimos años. A continuación se
presenta un procedimiento para reemplazar integradores clásicos por integradores
referidos a la fase, incluyendo un ejemplo de diseño de un
modulador Sigma-Delta de segundo orden basado en osciladores. Posteriormente
se describen los principales problemas que limitan el rendimiento de este
tipo de sistemas, como el ruido de fase, el jitter o la metaestabilidad.
Esta tesis también presenta un nuevo método para evaluar el impacto
del ruido de fase y de la distorsión en sistemas basados en osciladores. El
método propuesto está basado en simulaciones PSS, las cuales permiten
la rápida estimación del rango dinámico del sistema sin necesidad de
recurrir a simulaciones temporales. Además, este trabajo describe una
nueva técnica para analizar el impacto del jitter de reloj en moduladores Sigma-Delta.
En esta tesis se han implementado dos circuitos integrados en tecnología
CMOS de 0.13 μm, con el fin de demostrar la viabilidad de los
moduladores Sigma-Delta de alto orden basados en osciladores. Ambos chips han
sido diseñados para producir conformación espectral de ruido de segundo
orden, usando únicamente osciladores y circuitos mayoritariamente digitales.
El primer chip ha mostrado un error en el funcionamiento de los
circuitos digitales debido a la complejidad de las estructuras multi-bit
utilizadas. El segundo chip, implementado usando contadores de un solo
bit con el fin de simplificar el sistema, consigue conformación espectral
de ruido de segundo orden y alcanza 103 dB-A de rango dinámico en el
ancho de banda del audio, ocupando solo 0.04 mm2.Programa Oficial de Doctorado en Ingeniería Eléctrica, Electrónica y AutomáticaPresidente: Georges G.E. Gielen.- Secretario: José Manuel de la Rosa.- Vocal: Ana Rus
Time-encoding analog-to-digital converters : bridging the analog gap to advanced digital CMOS? Part 2: architectures and circuits
The scaling of CMOS technology deep into the nanometer range has created challenges for the design of highperformance analog ICs: they remain large in area and power consumption in spite of process scaling. Analog circuits based on time encoding [1], [2], where the signal information is encoded in the waveform transitions instead of its amplitude, have been developed to overcome these issues. While part one of this overview article [3] presented the basic principles of time encoding, this follow-up article describes and compares the main time-encoding architectures for analog-to-digital converters (ADCs) and discusses the corresponding design challenges of the circuit blocks. The focus is on structures that avoid, as much as possible, the use of traditional analog blocks like operational amplifiers (opamps) or comparators but instead use digital circuitry, ring oscillators, flip-flops, counters, an so on. Our overview of the state of the art will show that these circuits can achieve excellent performance. The obvious benefit of this highly digital approach to realizing analog functionality is that the resulting circuits are small in area and more compatible with CMOS process scaling. The approach also allows for the easy integration of these analog functions in systems on chip operating at "digital" supply voltages as low as 1V and lower. A large part of the design process can also be embedded in a standard digital synthesis flow
Architectural Alternatives to Implement High-Performance Delta-Sigma Modulators
RÉSUMÉ Le besoin d’appareils portatifs, de téléphones intelligents et de systèmes microélectroniques implantables médicaux s’accroît remarquablement. Cependant, l’optimisation de l’alimentation de tous ces appareils électroniques portables est l’un des principaux défis en raison du manque de piles à grande capacité utilisées pour les alimenter. C’est un fait bien établi que le convertisseur analogique-numérique (CAN) est l’un des blocs les plus critiques de ces appareils et qu’il doit convertir efficacement les signaux analogiques au monde numérique pour effectuer un post-traitement tel que l’extraction de caractéristiques. Parmi les différents types de CAN, les modulateurs Delta Sigma (��M) ont été utilisés dans ces appareils en raison des fonctionnalités alléchantes qu’ils offrent. En raison du suréchantillonnage et pour éloigner le bruit de la bande d’intérêt, un CAN haute résolution peut être obtenu avec les architectures ��. Il offre également un compromis entre la fréquence d’échantillonnage et la résolution, tout en offrant une architecture programmable pour réaliser un CAN flexible. Ces CAN peuvent être implémentés avec des blocs analogiques de faible précision. De plus, ils peuvent être efficacement optimisés au niveau de l’architecture et circuits correspondants. Cette dernière caractéristique a été une motivation pour proposer différentes architectures au fil des ans. Cette thèse contribue à ce sujet en explorant de nouvelles architectures pour optimiser la structure ��M en termes de résolution, de consommation d’énergie et de surface de silicium. Des soucis particuliers doivent également être pris en compte pour faciliter la mise en œuvre du ��M. D’autre part, les nouveaux procédés CMOS de conception et fabrication apportent des améliorations remarquables en termes de vitesse, de taille et de consommation d’énergie lors de la mise en œuvre de circuits numériques. Une telle mise à l’échelle agressive des procédés, rend la conception de blocs analogiques tel que un amplificateur de transconductance opérationnel (OTA), difficile. Par conséquent, des soins spéciaux sont également pris en compte dans cette thèse pour surmonter les problèmes énumérés. Ayant mentionné ci-dessus que cette thèse est principalement composée de deux parties principales. La première concerne les nouvelles architectures implémentées en mode de tension et la seconde partie contient une nouvelle architecture réalisée en mode hybride tension et temps.----------ABSTRACT The need for hand-held devices, smart-phones and medical implantable microelectronic sys-tems, is remarkably growing up. However, keeping all these electronic devices power optimized is one of the main challenges due to the lack of long life-time batteries utilized to power them up. It is a well-established fact that analog-to-digital converter (ADC) is one of the most critical building blocks of such devices and it needs to efficiently convert analog signals to the digital world to perform post processing such as channelizing, feature extraction, etc. Among various type of ADCs, Delta Sigma Modulators (��Ms) have been widely used in those devices due to the tempting features they offer. In fact, due to oversampling and noise-shaping technique a high-resolution ADC can be achieved with �� architectures. It also offers a compromise between sampling frequency and resolution while providing a highly-programmable approach to realize an ADC. Moreover, such ADCs can be implemented with low-precision analog blocks. Last but not the least, they are capable of being effectively power optimized at both architectural and circuit levels. The latter has been a motivation to proposed different architectures over the years.This thesis contributes to this topic by exploring new architectures to effectively optimize the ��M structure in terms of resolution, power consumption and chip area. Special cares must also be taken into account to ease the implementation of the ��M. On the other hand, advanced node CMOS processes bring remarkable improvements in terms of speed, size and power consumption while implementing digital circuits. Such an aggressive process scaling, however, make the design of analog blocks, e.g. operational transconductance amplifiers (OTAs), cumbersome. Therefore, special cares are also taken into account in this thesis to overcome the mentioned issues. Having had above mentioned discussion, this thesis is mainly split in two main categories. First category addresses new architectures implemented in a pure voltage domain and the second category contains new architecture realized in a hybrid voltage and time domain. In doing so, the thesis first focuses on a switched-capacitor implementation of a ��M while presenting an architectural solution to overcome the limitations of the previous approaches. This limitations include a power hungry adder in a conventional feed-forward topology as well as power hungry OTAs
Design of sigma-delta modulators for analog-to-digital conversion intensively using passive circuits
This thesis presents the analysis, design implementation and experimental evaluation of passiveactive discrete-time and continuous-time Sigma-Delta (ΣΔ) modulators (ΣΔMs) analog-todigital converters (ADCs).
Two prototype circuits were manufactured. The first one, a discrete-time 2nd-order ΣΔM, was designed in a 130 nm CMOS technology. This prototype confirmed the validity of the ultra incomplete settling (UIS) concept used for implementing the passive integrators. This circuit, clocked at 100 MHz and consuming 298 μW, achieves DR/SNR/SNDR of 78.2/73.9/72.8 dB, respectively, for a signal bandwidth of 300 kHz. This results in a Walden FoMW of 139.3 fJ/conv.-step and Schreier FoMS of 168 dB.
The final prototype circuit is a highly area and power efficient ΣΔM using a combination of a cascaded topology, a continuous-time RC loop filter and switched-capacitor feedback paths. The modulator requires only two low gain stages that are based on differential pairs. A systematic design methodology based on genetic algorithm, was used, which allowed decreasing the circuit’s sensitivity to the circuit components’ variations. This continuous-time, 2-1 MASH ΣΔM has been designed in a 65 nm CMOS technology and it occupies an area of just 0.027 mm2. Measurement results show that this modulator achieves a peak SNR/SNDR of 76/72.2 dB and DR of 77dB for an input signal bandwidth of 10 MHz, while dissipating 1.57 mW from a 1 V power supply voltage. The ΣΔM achieves a Walden FoMW of 23.6 fJ/level and a Schreier FoMS of 175 dB. The innovations proposed in this circuit result, both, in the reduction of the power consumption and of the chip size. To the best of the author’s knowledge the circuit achieves the lowest Walden FOMW for ΣΔMs operating at signal bandwidth from 5 MHz to 50 MHz reported to date
A 0.2 V 0.44 µW 20 kHz Analog to Digital Σ∆ Modulator with 57 fJ/conversion FoM
This paper presents a 90 nm CMOS A/D modulator operating with a supply voltage of 0.2 V, well below the threshold voltage of the transistors. The modulator is an open-loop first-order architecture based on a frequency-modulated intermediate signal, generated in a ring voltage-controlled oscillator. The linearity of the modulator is greatly improved by the adoption of a so-called soft-rail in the oscillator. Measurements show a dynamic range of 52 dB over a 20 kHz signal bandwidth with a sampling frequency of 3.4 MHz, for a total power consumption as low as 0.44 muW. The corresponding peak SNDR is 44.2 dB, while the peak SNR is 47.4 d
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