Design and Noise Analysis of a Novel Auto-Zeroing Structure for Continuous-Time Instrumentation Amplifiers

This paper introduces a low-noise, low-power amplifier for high-impedance sensors. An innovative circuit using an auto-zeroed architecture combined with frequency modulation to reject offset and low-frequency noise is proposed and analysed. Special care was given to avoid broadband noise aliasing and chopping in the signal path, and to minimize both the resulting equivalent input offset voltage and equivalent input biasing current. The theoretical noise analysis of the proposed topology covers most of the noise sources of the circuit. Simulations show that the input-referred noise level of the circuit is 13.4nV/pHz for a power consumption of 85μA with a power supply from 1.8V to 3.6V

Low-Noise Micro-Power Amplifiers for Biosignal Acquisition

There are many different types of biopotential signals, such as action potentials (APs), local field potentials (LFPs), electromyography (EMG), electrocardiogram (ECG), electroencephalogram (EEG), etc. Nerve action potentials play an important role for the analysis of human cognition, such as perception, memory, language, emotions, and motor control. EMGs provide vital information about the patients which allow clinicians to diagnose and treat many neuromuscular diseases, which could result in muscle paralysis, motor problems, etc. EEGs is critical in diagnosing epilepsy, sleep disorders, as well as brain tumors. Biopotential signals are very weak, which requires the biopotential amplifier to exhibit low input-referred noise. For example, EEGs have amplitudes from 1 μV [microvolt] to 100 μV [microvolt] with much of the energy in the sub-Hz [hertz] to 100 Hz [hertz] band. APs have amplitudes up to 500 μV [microvolt] with much of the energy in the 100 Hz [hertz] to 7 kHz [hertz] band. In wearable/implantable systems, the low-power operation of the biopotential amplifier is critical to avoid thermal damage to surrounding tissues, preserve long battery life, and enable wirelessly-delivered or harvested energy supply. For an ideal thermal-noise-limited amplifier, the amplifier power is inversely proportional to the input-referred noise of the amplifier. Therefore, there is a noise-power trade-off which must be well-balanced by the designers. In this work I propose novel amplifier topologies, which are able to significantly improve the noise-power efficiency by increasing the effective transconductance at a given current. In order to reject the DC offsets generated at the tissue-electrode interface, energy-efficient techniques are employed to create a low-frequency high-pass cutoff. The noise contribution of the high-pass cutoff circuitry is minimized by using power-efficient configurations, and optimizing the biasing and dimension of the devices. Sufficient common-mode rejection ratio (CMRR) and power supply rejection ratio (PSRR) are achieved to suppress common-mode interferences and power supply noises. Our design are fabricated in standard CMOS processes. The amplifiers’ performance are measured on the bench, and also demonstrated with biopotential recordings

Ultra-low power mixed-signal frontend for wearable EEGs

Electronics circuits are ubiquitous in daily life, aided by advancements in the chip design industry, leading to miniaturised solutions for typical day to day problems. One of the critical healthcare areas helped by this advancement in technology is electroencephalography (EEG). EEG is a non-invasive method of tracking a person's brain waves, and a crucial tool in several healthcare contexts, including epilepsy and sleep disorders. Current ambulatory EEG systems still suffer from limitations that affect their usability. Furthermore, many patients admitted to emergency departments (ED) for a neurological disorder like altered mental status or seizures, would remain undiagnosed hours to days after admission, which leads to an elevated rate of death compared to other conditions. Conducting a thorough EEG monitoring in early-stage could prevent further damage to the brain and avoid high mortality. But lack of portability and ease of access results in a long wait time for the prescribed patients. All real signals are analogue in nature, including brainwaves sensed by EEG systems. For converting the EEG signal into digital for further processing, a truly wearable EEG has to have an analogue mixed-signal front-end (AFE). This research aims to define the specifications for building a custom AFE for the EEG recording and use that to review the suitability of the architectures available in the literature. Another critical task is to provide new architectures that can meet the developed specifications for EEG monitoring and can be used in epilepsy diagnosis, sleep monitoring, drowsiness detection and depression study. The thesis starts with a preview on EEG technology and available methods of brainwaves recording. It further expands to design requirements for the AFE, with a discussion about critical issues that need resolving. Three new continuous-time capacitive feedback chopped amplifier designs are proposed. A novel calibration loop for setting the accurate value for a pseudo-resistor, which is a crucial block in the proposed topology, is also discussed. This pseudoresistor calibration loop achieved the resistor variation of under 8.25%. The thesis also presents a new design of a curvature corrected bandgap, as well as a novel DDA based fourth-order Sallen-Key filter. A modified sensor frontend architecture is then proposed, along with a detailed analysis of its implementation. Measurement results of the AFE are finally presented. The AFE consumed a total power of 3.2A (including ADC, amplifier, filter, and current generation circuitry) with the overall integrated input-referred noise of 0.87V-rms in the frequency band of 0.5-50Hz. Measurement results confirmed that only the proposed AFE achieved all defined specifications for the wearable EEG system with the smallest power consumption than state-of-art architectures that meet few but not all specifications. The AFE also achieved a CMRR of 131.62dB, which is higher than any studied architectures.Open Acces

High-precision fluorescence photometry for real-time biomarkers detection

Les derniers évènements planétaires et plus particulièrement l'avènement sans précédent du nouveau coronavirus augmente la demande pour des appareils de test à proximité du patient. Ceux-ci fonctionnent avec une batterie et peuvent identifier rapidement des biomarqueurs cibles. Pareils systèmes permettent aux utilisateurs, disposant de connaissances limitées en la matière, de réagir rapidement, par exemple dans la détection d'un cas positif de COVID-19. La mise en œuvre de l'élaboration d'un tel instrument est un projet multidisciplinaire impliquant notamment la conception de circuits intégrés, la programmation, la conception optique et la biologie, demandant tous une maîtrise pointue des détails. De plus, l'établissement des spécifications et des exigences pour mesurer avec précision les interactions lumière-échantillon s'additionnent au besoin d'expérience dans la conception et la fabrication de tels systèmes microélectriques personnalisés et nécessitent en elles-mêmes, une connaissance approfondie de la physique et des mathématiques. Ce projet vise donc à concevoir et à mettre en œuvre un appareil sans fil pour détecter rapidement des biomarqueurs impliqués dans des maladies infectieuses telles que le COVID-19 ou des types de cancers en milieu ambulatoire. Cette détection se fait grâce à des méthodes basées sur la fluorescence. La spectrophotométrie de fluorescence permet aux médecins d'identifier la présence de matériel génétique viral ou bactérien tel que l'ADN ou l'ARN et de les caractériser. Les appareils de paillasse sont énormes et gourmand énergétiquement tandis que les spectrophotomètres à fluorescence miniatuarisés disponibles dans le commerce sont confrontés à de nombreux défis. Ces appareils miniaturisés ont été découverts en tirant parti des diodes électroluminescentes (DEL) à semi-conducteurs peu coûteuses et de la technologie des circuits intégrés. Ces avantages aident les scientifiques à réduire les erreurs possibles, la consommation d'énergie et le coût du produit final utilisé par la population. Cependant, comme leurs homologues de paillasse, ces appareils POC doivent quantifier les concentrations en micro-volume d'analytes sur une large gamme de longueurs d'onde suivant le cadre d'une économie en ressources. Le microsystème envisagé bénéficie d'une approche de haute précision pour fabriquer une puce microélectronique CMOS. Ce procédé se fait de concert avec un boîtier personnalisé imprimé en 3D pour réaliser le spectrophotomètre à la fluorescence nécessaire à la détection quantitative d'analytes en microvolume. En ce qui a trait à la conception de circuits, une nouvelle technique de mise à auto-zeroing est appliquée à l'amplificateur central, celui-ci étant linéarisé avec des techniques de recyclage et de polarisation adaptative. Cet amplificateur central est entièrement différentiel et est utilisé dans un amplificateur à verrouillage pour récupérer le signal d'intérêt éclipsé par le bruit. De plus, l'augmentation de la sensibilité de l'appareil permet des mesures quantitatives avec des concentrations en micro-volume d'analytes ayant moins d'erreurs de prédiction de concentration. Cet avantage cumulé à une faible consommation d'énergie, un faible coût, de petites dimensions et un poids léger font de notre appareil une solution POC prometteuse dans le domaine de la spectrophotométrie de fluorescence. La validation de ce projet s'est fait en concevant, fabriquant et testant un prototype discret et sans fil. Son article de référence a été publié dans IEEE LSC 2018. Quant à la caractérisation et l'interprétation du prototype d'expériences in vitro à l'aide d'une interface MATLAB personnalisée, cet article a été publié dans IEEE Sensors journal (2021). Les circuits intégrés et les photodétecteurs ont été fabriqués ont été conçus et fabriqués par Cadence en 2019. Relativement aux solutions de circuit proposées, elles ont été fabriquées avec la technologie CMOS 180 nm et publiées lors de la conférence IEEE MWSCAS 2020. Tout comme cette dernière contribution, les expériences in vitro avec le dispositif proposé incluant la puce personnalisée et le boîtier imprimé en 3D ont été réalisés et les résultats électriques et optiques ont été soumis au IEEE Journal of Solid-State Circuits (JSSC 2022).The most recent and unprecedented experience of the novel coronavirus increases the demand for battery-operated near-patient testing devices that can rapidly identify the target biomarkers. Such systems enable end-users with limited resources to quickly get feedback on various medical tests, such as detecting positive COVID-19 cases. Implementing such a device is a multidisciplinary project dealing with multiple areas of expertise, including integrated circuit design, programming, optical design, and biology, each of which needs a firm grasp of details. Alongside the need for experience in designing and manufacturing custom microelectronic systems, establishing the specifications and requirements to precisely measure the light-sample interactions requires an in-depth knowledge of physics and mathematics. This project aims to design and implement a wireless point-of-care (POC) device to rapidly detect biomarkers involved in infectious diseases such as COVID-19 or different types of cancers in an ambulatory setting using fluorescence-based methods. Fluorescence spectrophotometry allows physicians to identify and characterize viral or bacterial genetic materials such as DNAs or RNAs. The benchtop devices that are currently available are bulky and power-hungry, whereas the commercially available miniaturized fluorescence spectrophotometers are facing many challenges. Many of these difficulties have been resolved in literature thanks to inexpensive semiconductor light-emitting diodes (LEDs) and integrated circuits technology. Such advantages aid scientists in decreasing the size, power consumption, and cost of the final product for end-users. However, like the benchtop counterparts, such POC devices must quantify micro-volume concentrations of analytes across a wide wave length range under an economy of resources. The envisioned microsystem benefits from a high-precision approach to fabricating a CMOS microelectronic chip combined with a custom 3D-printed housing. This implementation results in a fluorescence spectrophotometer for qualitative and quantitative detection of micro-volume analytes. In terms of circuit design, a novel switched-biasing ping-pong auto-zeroed technique is applied to the core amplifier, linearized with recycling and adaptive biasing techniques. The fully differential core amplifier is utilized within a lock-in amplifier to retrieve the signal of interest overshadowed by noise. Increasing the device's sensitivity allows quantitative measurements down to micro-volume concentrations of analytes with less concentration prediction error. Such an advantage, along with low-power consumption, low cost, low weight, and small dimensions, make our device a promising POC solution in the fluorescence spectrophotometry area. The approach of this project was validated by designing, fabricating, and testing a discrete and wireless prototype. Its conference paper was published in IEEE LSC 2018, and the prototype characterization and interpretation of in vitro experiments using a custom MATLAB interface were published in IEEE Sensors Journal (2021). The integrated circuits and photodetectors were designed and fabricated by the Cadence circuit design toolbox (2019). The proposed circuit solutions were fabricated with 180-nm CMOS technology and published at IEEE MWSCAS 2020 conference. As the last contribution, the in vitro experiments with the proposed device, including the custom chip and 3D-printed housing, were performed, and the electrical and optical results were submitted to the IEEE Journal of Solid-State Circuits (JSSC 2022)

Design of a CMOS chopper instrumentation amplifier with rail-to-rail input and output ranges

This thesis deals with the design of a current feedback instrumentation amplifier, optimized for the readout of thermal sensors. This topology stands out for its excellent CMRR and the predisposition to feature low frequency error reduction techniques. Versatility is a main target for this work: 1 kHz bandwidth and Rail-To-Rail input common mode range allow the readout of a wide variety of sensors. Chopper modulation is used to reduce offset and flicker noise, achieving a 19 nV/sqrt(Hz) RTI noise density and a flicker corner frequency of less than 10 mHz. A low total output noise power is achieved as well, reaching an ENOB of 12 bits with less than 350 µA current consumption. The peculiar issue for this architecture, that is gain error, is solved by means of Port Swapping technique, together with an input Common Mode Equalization. Chopped offset and Port Swapping ripple are completely filtered away by a third order Butterworth State Variable low pass filter, implemented with Gm-C integrators

LOW POWER AND HIGH SIGNAL TO NOISE RATIO BIO-MEDICAL AFE DESIGN TECHNIQUES

The research work described in this thesis was focused on finding novel techniques to implement a low-power and noise Bio-Medical Analog Front End (BMEF) circuit technique to enable high-quality Electrocardiography (ECG) sensing. Usually, an ECG signal and several bio-medical signals are sensed from the human body through a pair of electrodes. The electrical characteristics of the very small amplitude (1u-10mV) signals are corrupted by random noise and have a significant dc offset. 50/60Hz power supply coupling noise is one of the biggest cross-talk signals compared to the thermally generated random noise. These signals are even AFE composed of an Instrumentation Amplifier (IA), which will have a better Common Mode rejection ratio (CMRR). The main function of the AFE is to convert the weak electrical Signal into large signals whose amplitude is large enough for an Analog Digital Converter (ADC) to detect without having any errors. A Variable Gain Amplifier (VGA) is sometimes required to adjust signal amplitude to maintain the dynamic range of the ADC. Also, the Bio-medical transceiver needs an accurate and temperature-independent reference voltage and current for the ADC, commonly known as Bandgap Reference Circuit (BGR). These circuits need to consume as low power as possible to enable these circuits to be powered from the battery. The work started with analysing the existing circuit techniques for the circuits mentioned above and finding the key important improvements required to reach the target specifications. Previously proposed IA is generated based on voltage mode signal processing. To improve the CMRR (119dB), we proposed a current mode-based IA with an embedded DC cancellation technique. State-of-the-art VGA circuits were built based on the degeneration principle of the differential pair, which will enable the variable gain purpose, but none of these techniques discussed linearity improvement, which is very important in modern CMOS technologies. This work enhances the total Harmonic distortion (THD) by 21dB in the worst case by exploiting the feedback techniques around the differential pair. Also, this work proposes a low power curvature compensated bandgap with 2ppm/0C temperature sensitivity while consuming 12.5uW power from a 1.2V dc power supply. All circuits were built in 45nm TSMC-CMOS technology and simulated with all the performance metrics with Cadence (spectre) simulator. The circuit layout was carried out to study post-layout parasitic effect sensitivity

Progetto di un amplificatore da strumentazione CMOS con consumo e rumore programmabili

In questo lavoro di tesi è stato progettato un amplificatore da strumentazione capace di interfacciarsi a diverse tipologie di sensori al fine di implementare in un unico microsistema integrato sia le strutture di sensing sia l’elettronica di condizionamento. L’amplificatore è stato realizzato in tecnologia CMOS mediante il processo BCD6s della STMicroelectronics. La progettazione full-custom ha comportato la scelta della topologia, il dimensionamento dei dispositivi, la simulazione dell’intero sistema e il layout delle celle che compongono l’InAmp. La scelta di due possibili configurazioni di consumo e di rumore permette di coprire diverse esigenze a seconda dell’applicazione. Per ridurre il rumore introdotto dal sistema alle frequenze di interesse (dalla DC fino ad un centinaio di hertz) è stato necessario adottare la modulazione chopper, una tecnica molto diffusa per la cancellazione dell’offset e del rumore flicker. La topologia utilizzata per l’InAmp prevede la cascata di due stadi integratori G_m/C chiusi in reazione in modo tale da ottenere una funzione di trasferimento passa basso del secondo ordine di tipo Butterworth (con frequenza di taglio uguale a 200 Hz). Il guadagno, determinato dalla rete di feedback attraverso un partitore resistivo, è stato fissato al valore di 201. Per aumentare la precisione sul guadagno abbiamo adottato la tecnica “port swapping” nel modulatore di ingresso per ridurre l’errore provocato dalle resistenze di sorgente e dalle capacità di ingresso, e utilizzato un modulatore di feedback per evitare che un mismatch tra le resistenze in reazione generi un segnale differenziale indesiderato in ingresso al sistema. Nella configurazione a basso consumo di potenza il rumore dovuto all’InAmp è pari a 20 nV/√Hz e la corrente assorbita risulta di 171.5 µA. Nella configurazione ad alto consumo di potenza si ha una migliore prestazione sul rumore con un valore di 13 nV/√Hz, a discapito della corrente assorbita che risulta maggiore intorno a 456.5 µA. Un’innovazione introdotta nell’amplificatore proposto consiste nell’inserimento di un circuito di controllo del modo comune del segnale di feedback, necessario per il corretto funzionamento dell’InAmp in un range della tensione di modo comune di ingresso che va da 0.7 V fino a 2.2 V. La dinamica differenziale di ingresso varia da -6 mV a +6 mV. L’area occupata dall’intero sistema è stata stimata intorno a 1125 x 620 µm². Lo sviluppo futuro prevede il layout finale con il placing delle celle ed il relativo routing dei collegamenti e la fabbricazione del chip per la realizzazione di un flussimetro termico integrato

Durcissement par conception d'ASIC analogiques

The purpose of this thesis work is to investigate circuit design techniques to improve the robustness to Total Ionizing Dose (TID) of analog circuits within electronic systems embedded in space probes, satellites and vehicles. Such circuits often contain bipolartransistor components which are quite sensitive to cumulated radiation dose. However highly integrated CMOS technology has been shown to exhibit better natural TDI hardening.The approach proposed here is a hardening by design using a full CMOS semiconductor technology commercially available from ST Microelectronics calledHCMOS9A. The proposed generic hardening design methods will be seen to be compatibleand applicable to other existing or future process technologies. Furthermore this approach addresses the issue of ever-increasing development cost and access to hardened technologies.The first TID hardening technique proposed is applied to a full-CMOS voltage reference. This technique does not involve p-n junctions nor any particular layout precaution but instead is based on the subtraction of two different threshold voltages which allows the cancellation of TDI effects. While the use of advanced commercial CMOS technologies for specific radiation hardened applications is becoming more common, these technologies suffer from larger inputoffs et voltage drift than their bipolar transistor counterparts, which can impact system performance. The second technique studied is that of auto-zeroing, which is an efficient method to reduce the complex offset voltage drift mechanisms of operational amplifiers due to temperature. The purpose here is to prove that this technique can also cancel input offset voltage drift due to TID.Index term : hardening, cumulated dose, CMOS technology, voltage reference,operational amplifier.Les travaux de cette thèse sont axés sur le durcissement à la dose cumulée des circuits analogiques associés aux systèmes électroniques embarqués sur des véhicules spatiaux, satellites ou sondes. Ces types de circuits sont réputés pour être relativement sensibles à la dose cumulée, parfois dès quelques krad, souvent en raison de l’intégration d’éléments bipolaires. Les nouvelles technologies CMOS montrent par leur intégration de plus en plus poussée, un durcissement naturel à cette dose. L’approche de durcissement proposée ici, repose sur un durcissement par la conception d’une technologie commerciale « full CMOS » du fondeur ST Microelectronics, appelée HCMOS9A. Cette approche permet d’assurer la portabilité des méthodes de durcissement proposées d’une technologie à une autre et de rendre ainsi accessible les nouvelles technologies aux systèmes spatiaux. De plus, cette approche de durcissement permet de faire face aux coûts croissants de développement et d’accès aux technologies durcies. Une première technique de durcissement à la dose cumulée est appliquée à une tension de référence « full CMOS ». Elle ne fait intervenir ni jonction p-n parasites ni précautions delay out particulières mais la soustraction de deux tensions de seuil qui annulent leurs effets à la dose cumulée entre elles. Si les technologies commerciales avancées sont de plus en plus utilisées pour des applications spécialement durcies, ces dernières exhibent en contrepartie de plus grands offsets que les technologies bipolaires. Cela peut affecter les performances des systèmes. La seconde technique étudiée : l’auto zéro, est une solution efficace pour réduire les dérives complexes dues entre autres à la température, de l’offset d’entrée des amplificateurs opérationnels. Le but ici est de prouver que cette technique peut tout aussi bien contrebalancer les dérives de l’offset dues à la dose cumulée

Design of agile signal conditioning circuits for microelectromechanical sensors

Microelectromechanical systems (MEMS) are used in many applications to detect physical parameters and convert them to an electrical signal. The output of MEMS-based transducers is usually not suitable to be directly processed in the digital or the analog domain, and they could be as small as femto farads in capacitive sensing and micro volts in resistive sensing. Consequently, high sensitivity signal conditioning circuits are essential. In this thesis, it is shown that both the noise and input capacitance are important parameters to ensure optimal capacitive sensing. The dominant noise source in MEMS conditioning circuits is flicker noise, and one of the best methods to mitigate flicker noise is the chopping technique. Three different chopping techniques are considered: single chopper amplifier (SCA), dual chopper amplifier (DCA), and two-stage single chopper amplifier (TCA). Also, their sensitivity and power consumption based on the total gain and sensing capacitance are extracted. It is shown that the distribution of gain between the two stages in the DCA and TCA has a significant effect on the sensitivity, and, based on this distribution, the sensitivity and power consumption change significantly. For small sensor capacitances, the highest sensitivity could be achieved by a DCA because of its ability to decrease the noise floor and the input sensor capacitance simultaneously. A novel DCA is proposed to reach higher sensitivity and reduced power consumption. In this DCA, two supply voltages are utilized, and the second stage is composed of two parallel paths that improve the SNR and provide two gain settings. This circuit is fabricated in the GlobalFoundries 0.13 μm CMOS technology. The measurement results show a power consumption of 2.66 μW for the supply voltage of 0.7 V and of 3.26 μW for the supply voltage of 1.2 V. The single path DCA has a gain of 34 dB with bandwidth of 4 kHz and input noise floor of 25 nV/√Hz. The dual path DCA has a gain of 38 dB with bandwidth of 3 kHz and input noise floor of 40 nV/√Hz. To be able to detect the signal near DC frequencies, another circuit is proposed which has a configurable bandwidth and a sub-μHz noise corner frequency. This circuit is composed of three stages, and three chopping frequencies are used to mitigate the flicker noise of the three stages. The simulated circuit is designed in the GlobalFoundries 0.13 μm CMOS technology with supply voltages of 0.4 V and 1.2 V. The total power consumption is of 6.7 μW. A gain of 68 dB and bandwidths of 1, 10, 100 and 1000 Hz are achieved. The input referred noise floor is of 20.5 nV/√Hz and the design attains a good power efficiency factor of 4.0. In the capacitive mode, the noise floor is of 3.6 zF for a 100 fF capacitance sensor