High frequency of low noise amplifier architecture for WiMAX application: A review

The low noise amplifier (LNA) circuit is exceptionally imperative as it promotes and initializes general execution performance and quality of the mobile communication system. LNA's design in radio frequency (R.F.) circuit requires the trade-off numerous imperative features' including gain, noise figure (N.F.), bandwidth, stability, sensitivity, power consumption, and complexity. Improvements to the LNA's overall performance should be made to fulfil the worldwide interoperability for microwave access (WiMAX) specifications' prerequisites. The development of front-end receiver, particularly the LNA, is genuinely pivotal for long-distance communications up to 50 km for a particular system with particular requirements. The LNA architecture has recently been designed to concentrate on a single transistor, cascode, or cascade constrained in gain, bandwidth, and noise figure

A 0.13-μm Cmos Reconfigurable Power Constrained Simultaneous Noise And Input Matching (Pcsnim) Low Noise Amplifier (Lna) For Multi-Standard 0.9, 1.8 And 2.1 Ghz Mobile Application

Industri komunikasi tanpa wayar sedang mengalami pertumbuhan yang luar biasa. Sebelum ini, penerima berbilang piawaian telah direka dalam seni bina yang selari untuk menampung berbilang piawai. Walaubagaimanapun, untuk setiap laluan, kawasan bentangan yang besar membuatkan kos fabrikasi meningkat. Sebagai tindakbalas terhadap permintaan untuk bahagian hadapan tanpa wayar yang berkos rendah dan berprestasi lebih tinggi, banyak kajian intensif pada CMOS frekuensi radio (RF ) litar bahagian hadapan telah dijalankan. Projek ini menggabungkan laluan-laluan selari tersebut kepada kaedah penerima tanpa wayar laluan tunggal. Matlamat utama adalah untuk meminimumkan “trade-off” atau mencapai keseimbangan antara prestasi tinggi, saiz yang lebih kecil dan kos rendah pada reka bentuk penggunaan kuasa yang rendah. Sasaran projek ini adalah untuk mereka bentuk penguat hingar rendah (LNA) berbilang piawaian bagi tiga piawai operasi jalur frekuensi. Bagi mendemonstrasi keberkesanan teknik, satu reka bentuk LNA laluan tunggal berbilang piawaian menggunakan konsep pensuisan telah dilaksanakan. Reka bentuk boleh memilih jalur frekuensi operasi dengan mengalihkan suis yang digunakan di rangkaian padanan masukan dan keluaran. Satu LNA berbilang piawaian dengan topologi Padanan Masukan dan Hingar Serentak dengan Kekangan Kuasa (PCSNIM) telah dilaksanakan bagi tujuan ini. LNA beroperasi pada frekuensi 0.9 , 1.8 dan 2.1 GHz. Oleh itu, reka bentuk piawai tanpa wayar adalah bagi aplikasi GSM900 , DCS1800 dan W-CDMA. Reka bentuk ini telah dilaksanakan pada proses CMOS 0.13-μm 8-lapisan logam. LNA berbilang piawaian mempamerkan nilai angka hingar (NF) serendah 1.72 dB pada 1.8 GHz dan 1.85 dB pada 2.1 GHz. Gandaan adalah dalam julat 10 ke 11 dB. Titik pintasan tertib ketiga (IIP3) adalah setinggi 0.2 dBm (pada 1.8 GHz), -1 dBm (pada 2.1 GHz) dan -2 dBm (pada 0.9 GHz). Manakala titik mampatan 1 dB pula adalah -12.2 dBm (pada 0.9 GHz), -11.5 dBm (pada 1.8 GHz) dan -11 dBm (pada 2.1 GHz). Jumlah penggunaan kuasa untuk reka bentuk ini adalah 7.42 mW dengan bekalan voltan sebanyak 1.2 V. ________________________________________________________________________________________________________________________ The wireless communication industry is experiencing tremendous growth. Previously, multi-standard receivers were designed using parallel architecture to accommodate multiple standards. However, for each path, the area consumption is high which increases cost of fabrication. Responding to the demand for a low-cost and high performance wireless front-end, many intensive researches on CMOS radio-frequency (RF) front-end circuits have been carried out. This project merges the parallel paths into a single path wireless receiver. The ultimate goal is to minimize the trade-off between high performance, smaller size and low-cost at low power consumption design. The target of this project is to design a multi-standard low noise amplifier (LNA) for three standards frequency bands. To demonstrate the effectiveness of the design technique, an LNA design is presented for multi-standard single path LNA with the switching concept. The design can select operating frequency band by switching the switches which are adopted at the input and output matching network. A multi-standard Power Constrained Simultaneous Noise and Input Matching (PCSNIM) topology was implemented. The multi-standard LNA is operated at 0.9, 1.8 and 2.1 GHz frequencies. The design covers wireless standards of GSM900, DCS1800 and W-CDMA applications. The design was implemented on 0.13-μm 8- metal CMOS process. The multi-standard LNA shows the noise figure (NF) as low as 1.72 dB at 1.8 GHz and 1.85 dB at 2.1 GHz. The gain is in the range 10 up to 11 dB. The third order intercept point (IIP3) is 0.2 dBm (at 1.8 GHz), -1 dBm (at 2.1 GHz) and -2 dBm (at 0.9 GHz) while IP1dB compression point is -12.2 dBm (at 0.9 GHz), -11.5 dBm (at 1.8 GHz) and -11 dBm (at 2.1 GHz). The power consumption of the design is 7.42 mW with 1.2 V power supply

A New Application of Current Conveyors: The Design of Wideband Controllable Low-Noise Amplifiers

The aim of this paper is three-fold. First, it reviews the low-noise amplifier and its relevance in wireless communications receivers. Then it presents an exhaustive review of the existing topologies. Finally, it introduces a new class of LNAs, based on current conveyors, describing the founding principle and the performances of a new single-ended LNA. The new LNAs offer the following notable advantages: total absence of passive elements (and the smallest LNAs in their respective classes); wideband performance, with stable frequency responses from 0 to 3 GHz; easy gain control over wide ranges (0 to 20 dB). Comparisons with other topologies prove that the new class of LNA greatly advances the state of the art

High Performance RF and Basdband Analog-to-Digital Interface for Multi-standard/Wideband Applications

The prevalence of wireless standards and the introduction of dynamic standards/applications, such as software-defined radio, necessitate the next generation wireless devices that integrate multiple standards in a single chip-set to support a variety of services. To reduce the cost and area of such multi-standard handheld devices, reconfigurability is desirable, and the hardware should be shared/reused as much as possible. This research proposes several novel circuit topologies that can meet various specifications with minimum cost, which are suited for multi-standard applications. This doctoral study has two separate contributions: 1. The low noise amplifier (LNA) for the RF front-end; and 2. The analog-to-digital converter (ADC). The first part of this dissertation focuses on LNA noise reduction and linearization techniques where two novel LNAs are designed, taped out, and measured. The first LNA, implemented in TSMC (Taiwan Semiconductor Manufacturing Company) 0.35Cm CMOS (Complementary metal-oxide-semiconductor) process, strategically combined an inductor connected at the gate of the cascode transistor and the capacitive cross-coupling to reduce the noise and nonlinearity contributions of the cascode transistors. The proposed technique reduces LNA NF by 0.35 dB at 2.2 GHz and increases its IIP3 and voltage gain by 2.35 dBm and 2dB respectively, without a compromise on power consumption. The second LNA, implemented in UMC (United Microelectronics Corporation) 0.13Cm CMOS process, features a practical linearization technique for high-frequency wideband applications using an active nonlinear resistor, which obtains a robust linearity improvement over process and temperature variations. The proposed linearization method is experimentally demonstrated to improve the IIP3 by 3.5 to 9 dB over a 2.5–10 GHz frequency range. A comparison of measurement results with the prior published state-of-art Ultra-Wideband (UWB) LNAs shows that the proposed linearized UWB LNA achieves excellent linearity with much less power than previously published works. The second part of this dissertation developed a reconfigurable ADC for multistandard receiver and video processors. Typical ADCs are power optimized for only one operating speed, while a reconfigurable ADC can scale its power at different speeds, enabling minimal power consumption over a broad range of sampling rates. A novel ADC architecture is proposed for programming the sampling rate with constant biasing current and single clock. The ADC was designed and fabricated using UMC 90nm CMOS process and featured good power scalability and simplified system design. The programmable speed range covers all the video formats and most of the wireless communication standards, while achieving comparable Figure-of-Merit with customized ADCs at each performance node. Since bias current is kept constant, the reconfigurable ADC is more robust and reliable than the previous published works

Configurable circuits and their impact on multi-standard RF front-end architectures

This thesis studies configurable circuits and their impact on multi-standard RF front-end architectures. In particular, low-voltage low-power linear LNA and mixer topologies suitable for implementation in multi-standard front-ends are subject of the investigation. With respect to frequency and bandwidth, multi-standard front-ends can be implemented using either tunable or wideband LNA and mixer topologies. Based on the type of the LNA and mixer(s), multi-standard receiver RF front-ends can be divided into three groups. They can be (tunable) narrow-band, wide-band or combined. The advantages and disadvantages of the different multi-standard receiver RF front-ends have been discussed in detail. The partitioning between off-chip selectivity, on-chip selectivity provided by the LNA and mixer, linearity, power consumption and occupied chip area in each multi-standard RF front-end group are thoroughly investigated. A Figure of Merit (FOM) for the multi-standard receiver RF front-end has been introduced. Based on this FOM the most suitable multi-standard RF front-end group in terms of cost-effectiveness can be selected. In order to determine which multi-standard RF front-end group is the most cost-effective for a practical application, a GSM850/E-GSM/DCS/PCS/Bluetooth/WLANa/b/g multi-standard receiver RF front-end is chosen as a demonstrator. These standards are the most frequently used standards in wireless communication, and this combination of standards allows to users almost "anytime-anywhere" voice and data transfer. In order to verify these results, three demonstrators have been defined, designed and implemented, two wideband RF front-end circuits in 90nm CMOS and 65nm CMOS, and one combined multi-standard RF front-end circuit in 65nm CMOS. The proposed multi-standard demonstrators have been compared with the state-of the art narrow-band, wide-band and combined multi-standard RF front-ends. On the proposed multi-standard RF front-ends and the state-of the art multi-standard RF front-ends the proposed FOM have been applied. The comparison shows that the combined multi-standard RF front-end group is the most cost effective multi-standard group for this application

Low-Power Wake-Up Receivers

The Internet of Things (IoT) is leading the world to the Internet of Everything (IoE), where things, people, intelligent machines, data and processes will be connected together. The key to enter the era of the IoE lies in enormous sensor nodes being deployed in the massively expanding wireless sensor networks (WSNs). By the year of 2025, more than 42 billion IoT devices will be connected to the Internet. While the future IoE will bring priceless advantages for the life of mankind, one challenge limiting the nowadays IoT from further development is the ongoing power demand with the dramatically growing number of the wireless sensor nodes. To address the power consumption issue, this dissertation is motivated to investigate low-power wake-up receivers (WuRXs) which will significantly enhance the sustainability of the WSNs and the environmental awareness of the IoT. Two proof-of-concept low-power WuRXs with focuses on two different application scenarios have been proposed. The first WuRX, implemented in a cost-effective 180-nm CMOS semiconductor technology, operates at 401−406-MHz band. It is a good candidate for application scenarios, where both a high sensitivity and an ultra-low power consumption are in demand. Concrete use cases are, for instance, medical implantable applications or long-range communications in rural areas. This WuRX does not rely on a further assisting semiconductor technology, such as MEMS which is widely used in state-of-the-art WuRXs operating at similar frequencies. Thus, this WuRX is a promising solution to low-power low-cost IoT. The second WuRX, implemented in a 45-nm RFSOI CMOS technology, was researched for short-range communication applications, where high-density conventional IoT devices should be installed. By investigation of the WuRX for operation at higher frequency band from 5.5 GHz to 7.5 GHz, the nowadays ever more over-traffic issues that arise at low frequency bands such as 2.4 GHz can be substantially addressed. A systematic, analytical research route has been carried out in realization of the proposed WuRXs. The thesis begins with a thorough study of state-of-the-art WuRX architectures. By examining pros and cons of these architectures, two novel architectures are proposed for the WuRXs in accordance with their specific use cases. Thereon, key WuRX parameters are systematically analyzed and optimized; the performance of relevant circuits is modeled and simulated extensively. The knowledge gained through these investigations builds up a solid theoretical basis for the ongoing WuRX designs. Thereafter, the two WuRXs have been analytically researched, developed and optimized to achieve their highest performance. Proof-of-concept circuits for both the WuRXs have been fabricated and comprehensively characterized under laboratory conditions. Finally, measurement results have verified the feasibility of the design concept and the feasibility of both the WuRXs

HIGH LINEARITY UNIVERSAL LNA DESIGNS FOR NEXT GENERATION WIRELESS APPLICATIONS

Design of the next generation (4G) systems is one of the most active and important area of research and development in wireless communications. The 2G and 3G technologies will still co-exist with the 4G for a certain period of time. Other applications such as wireless LAN (Local Area Network) and RFID are also widely used. As a result, there emerges a trend towards integrating multiple wireless functionalities into a single mobile device. Low noise amplifier (LNA), the most critical component of the receiver front-end, determines the sensitivity and noise figure of the receiver and is indispensable for the complete system. To satisfy the need for higher performance and diversity of wireless communication systems, three LNAs with different structures and techniques are proposed in the thesis based on the 4G applications. The first LNA is designed and optimized specifically for LTE applications, which could be easily added to the existing system to support different standards. In this cascode LNA, the nonlinearity coming from the common source (CS) and common gate (CG) stages are analyzed in detail, and a novel linear structure is proposed to enhance the linearity in a relatively wide bandwidth. The LNA has a bandwidth of 900MHz with the linearity of greater than 7.5dBm at the central frequency of 1.2GHz. Testing results show that the proposed structure effectively increases and maintains linearity of the LNA in a wide bandwidth. However, a broadband LNA that covers multiple frequency ranges appears more attractive due to system simplicity and low cost. The second design, a wideband LNA, is proposed to cover multiple wireless standards, such as LTE, RFID, GSM, and CDMA. A novel input-matching network is proposed to relax the tradeoff among noise figure and bandwidth. A high gain (>10dB) in a wide frequency range (1-3GHz) and a minimum NF of 2.5dB are achieved. The LNA consumes only 7mW on a 1.2V supply. The first and second LNAs are designed mainly for the LTE standard because it is the most widely used standard in the 4G communication systems. However, WiMAX, another 4G standard, is also being widely used in many applications. The third design targets on covering both the LTE and the WiMAX. An improved noise cancelling technique with gain enhancing structure is proposed in this design and the bandwidth is enlarged to 8GHz. In this frequency range, a maximum power gain of 14.5dB and a NF of 2.6-4.3dB are achieved. The core area of this LNA is 0.46x0.67mm2 and it consumes 17mW from a 1.2V supply. The three designs in the thesis work are proposed for the multi-standard applications based on the realization of the 4G technologies. The performance tradeoff among noise, linearity, and broadband impedance matching are explored and three new techniques are proposed for the tradeoff relaxation. The measurement results indicate the techniques effectively extend the bandwidth and suppress the increase of the NF and nonlinearity at high frequencies. The three proposed structures can be easily applied to the wideband and multi-standard LNA design

System and Circuit Design Techniques for Silicon-based Multi-band/Multi-standard Receivers

Today, the advances in Complementary MetalOxideSemiconductor (CMOS) technology have guided the progress in the wireless communications circuits and systems area. Various new communication standards have been developed to accommodate a variety of applications at different frequency bands, such as cellular communications at 900 and 1800 MHz, global positioning system (GPS) at 1.2 and 1.5 GHz, and Bluetooth andWiFi at 2.4 and 5.2 GHz, respectively. The modern wireless technology is now motivated by the global trend of developing multi-band/multistandard terminals for low-cost and multifunction transceivers. Exploring the unused 10-66 GHz frequency spectrum for high data rate communication is also another trend in the wireless industry. In this dissertation, the challenges and solutions for designing a multi-band/multistandard mobile device is addressed from system-level analysis to circuit implementation. A systematic system-level design methodology for block-level budgeting is proposed. The system-level design methodology focuses on minimizing the power consumption of the overall receiver. Then, a novel millimeter-wave dual-band receiver front-end architecture is developed to operate at 24 and 31 GHz. The receiver relies on a newly introduced concept of harmonic selection that helps to reduce the complexity of the dual-band receiver. Wideband circuit techniques for millimeterwave frequencies are also investigated and new bandwidth extension techniques are proposed for the dual-band 24/31 GHz receiver. These new techniques are applied for the low noise amplifier and millimeter-wave mixer resulting in the widest reported operating bandwidth in K-band, while consuming less power consumption. Additionally, various receiver building blocks, such as a low noise amplifier with reconfigurable input matching network for multi-band receivers, and a low drop-out regulator with high power supply rejection are analyzed and proposed. The low noise amplifier presents the first one with continuously reconfigurable input matching network, while achieving a noise figure comparable to the wideband techniques. The low drop-out regulator presented the first one with high power supply rejection in the mega-hertz frequency range. All the proposed building blocks and architecture in this dissertation are implemented using the existing silicon-based technologies, and resulted in several publications in IEEE Journals and Conferences

An electronic neuromorphic system for real-time detection of High Frequency Oscillations (HFOs) in intracranial EEG

In this work, we present a neuromorphic system that combines for the first time a neural recording headstage with a signal-to-spike conversion circuit and a multi-core spiking neural network (SNN) architecture on the same die for recording, processing, and detecting High Frequency Oscillations (HFO), which are biomarkers for the epileptogenic zone. The device was fabricated using a standard 0.18$\mu$m CMOS technology node and has a total area of 99mm$^{2}$. We demonstrate its application to HFO detection in the iEEG recorded from 9 patients with temporal lobe epilepsy who subsequently underwent epilepsy surgery. The total average power consumption of the chip during the detection task was 614.3$\mu$W. We show how the neuromorphic system can reliably detect HFOs: the system predicts postsurgical seizure outcome with state-of-the-art accuracy, specificity and sensitivity (78%, 100%, and 33% respectively). This is the first feasibility study towards identifying relevant features in intracranial human data in real-time, on-chip, using event-based processors and spiking neural networks. By providing "neuromorphic intelligence" to neural recording circuits the approach proposed will pave the way for the development of systems that can detect HFO areas directly in the operation room and improve the seizure outcome of epilepsy surgery.Comment: 16 pages. A short video describing the rationale underlying the study can be viewed on https://youtu.be/NuAA91fdma