Heterogeneous 2.5D integration on through silicon interposer

© 2015 AIP Publishing LLC. Driven by the need to reduce the power consumption of mobile devices, and servers/data centers, and yet continue to deliver improved performance and experience by the end consumer of digital data, the semiconductor industry is looking for new technologies for manufacturing integrated circuits (ICs). In this quest, power consumed in transferring data over copper interconnects is a sizeable portion that needs to be addressed now and continuing over the next few decades. 2.5D Through-Si-Interposer (TSI) is a strong candidate to deliver improved performance while consuming lower power than in previous generations of servers/data centers and mobile devices. These low-power/high-performance advantages are realized through achievement of high interconnect densities on the TSI (higher than ever seen on Printed Circuit Boards (PCBs) or organic substrates), and enabling heterogeneous integration on the TSI platform where individual ICs are assembled at close proximity

Through Silicon Vias in MEMS packaging, a review

Trough Silicon Via (TSV) is a key enabling technology to achieve the integration of various dies by exploiting the third dimension. This allow the integration of heterogeneous chips in a single package (2.5D integration) or to achieve higher integration densities of transistors (3D integration). These vertical interconnections are widely used for both IC and MEMS devices. This paper reviews TSV technology focusing on their implementation in MEMS sensors with a broad overview on the various fabrication approaches and their constraints in terms of process compatibility. A case study of an inertial MEMS sensor will then be presented.publishedVersio

Study of the impact of lithography techniques and the current fabrication processes on the design rules of tridimensional fabrication technologies

Working for the photolithography tool manufacturer leader sometimes gives me the impression of how complex and specific is the sector I am working on. This master thesis topic came with the goal of getting the overall picture of the state-of-the-art: stepping out and trying to get a helicopter view usually helps to understand where a process is in the productive chain, or what other firms and markets are doing to continue improvingUniversidad de sevilla.Máster Universitario en Microelectrónica: Diseño y Aplicaciones de Sistemas Micro/Nanométrico

High Density Through Silicon Via (TSV)

The Through Silicon Via (TSV) process developed by Silex provides down to 30 micrometers pitch for through wafer connections in up to 600 micrometers thick substrates. Integrated with MEMS designs it enables significantly reduced die size and true "Wafer Level Packaging" - features that are particularly important in consumer market applications. The TSV technology also enables integration of advanced interconnect functions in optical MEMS, sensors and microfluidic devices. In addition the Via technology opens for very interesting possibilities considering integration with CMOS processing. With several companies using the process already today, qualified volume manufacturing in place and a line-up of potential users, the process is becoming a standard in the MEMS industry. We provide a introduction to the via formation process and also present some on the novel solutions made available by the technology.Comment: Submitted on behalf of EDA Publishing Association (http://irevues.inist.fr/handle/2042/16838

Numerical Modeling Analysis of Wafer Warpage and Carrier Mobility Change due to Tapered Through-Silicon-Via Geometry

Three-dimensional integration is a solution that vertically stacks multiple layers of silicon chips by Through-Silicon-Vias (TSVs) to enhance the performance of microelectronic devices. The tapered TSV profile can help to overcome the technical difficulties. However, an easily overlooked issue is that tapered TSV can cause wafer warpage during the fabrication processes. Wafer warpage can cause chip misalignment and impose additional deformation. In an effort to investigate the TSV geometric effect, a large number of finite element analysis (FEA) simulations were performed to quantify the thermal stress distribution and the thermally induced curvature. It was found that the tapered geometry alone can induce significant wafer bending, which has not been reported by other researchers. The effect of taper angle, TSV radius, TSV pitch, and wafer thickness were quantitatively studied. In addition, the incorporations of anisotropic silicon property and intermediate layers between the copper TSV and silicon into the numerical models were assessed. Thermally induced stress concentration around copper TSV near the wafer surface can lead to degradation of the device performance by affecting the carrier mobility in transistors. This piezoresistivity effect can cause serious reliability concerns. The size of keep-out zone (KOZ), which is identified as a threshold of 5% carrier mobility change, was also quantified for various transistor types in different channel directions

Optimization of through-silicon via structures in a fingerprint sensor package

The through-silicon via (TSV) is a type of vertical electrical connection that can pass through a silicon wafer or die. By using TSVs, compared to using wire bonding as interconnections in a capacitive fingerprint sensor, the capacitive strength between the sensor die and the finger can be increased. However, since TSV structures are both more complex as structures and have a more complex manufacturing process compared to wire bonding, reliability can be an issue. This thesis studies a TSV structure that failed qualification in where the aim was to find the root cause of the failure and to find how the material parameters affect the reliability of the TSV. A set of changes in process steps and materials used have been evaluated both by cross-section analysis and thermomechanical finite element analysis (FEA) simulations. The root cause of the failure could not fully be determined, but the cross-section analysis and FEA simulations showed that the usage of low coefficient of thermal expansion (CTE) polymers and high modulus trench fill could reduce the delamination ratio in the TSV.Integrating a fingerprint sensor under a smartphone’s cover glass As you may have noticed, the fingerprint sensor integrated in a smartphone is usually placed on the backside of the smartphone or inside the home button. Why is it that way and why can’t the sensor just be placed under the cover glass instead you may ask? This article will show how a capacitive fingerprint sensor can be integrated under glass and how the reliability of said technology can be improved. When the smartphone companies develop a new phone, the design is an important feature. The design is one of the deciding factors the consumers consider when they are choosing which model to buy since the smartphone is not only used as a phone, but also as an accessory. You might have noticed that Samsung’s model Galaxy S8 has a screen that covers the whole front of the phone. While the design of the screen looks very good, the fingerprint sensor was placed at an awkward position on the back of the phone. Why couldn’t the sensor just be integrated in the home button located under the glass? The answer to that question is that most fingerprint sensors in smartphones measures capacitance which is dependent on the distance between your finger and the sensor in where the cover glass is usually quite thick. To be able to do capacitive fingerprint sensing under glass, the distance between the sensor and the finger must be minimized. From the sensor die which performs the measurements, there need to be electrical connections to the phone. Usually this is done with wire bonding (Figure 1 b) in where tiny wires are used as interconnections. Since these wires are very thin they need to be protected, and this is usually done by applying a mold compound on top of the sensor die that covers the wires. However, this mold compound will add height on top of the sensor which will decrease the capacitive strength. Instead of wire bonding, through-silicon vias (TSV) (Figure 1 a) can be used as interconnections. The TSV is a type of vertical electrical connection that can pass through the sensor die in where no additional height is added on top of the sensor die. It is only recently that TSVs are available for mass production. By using TSVs, compared to using wire bonding as interconnections, the capacitive strength between the sensor die and the finger can be increased due to shorter separation distance. However, since TSV structures are both more complex as structures and have a more complex manufacturing process compared to wire bonding, reliability can be an issue. The reliability of the interconnects can be tested by exposing the sensor for a cycling temperature between -40 °C and 120 °C for several hundred cycles. This test will simulate a few years of normal phone usage. The TSV consists of many different layers with many different coefficients of thermal expansion (CTE). Some of these layers include a conducting copper layer and polymer layers which protect the copper layer. As the temperature cycles, all the layers will expand at different rates in which stress will be built up in the copper layer. Worst case scenario is that this copper layer will detach from the sensor die which will lead to premature failure of the sensor. Both simulations and cross-section analysis on TSV structures with different polymers show that the stress which is built up in the copper layer can be reduced by choosing polymers with low CTE. In that way, the sensor will have a longer life time. Next time you buy a smartphone you can notice that if the fingerprint sensor is located under a physical home button or on the backside, tiny wires are connecting the sensor to the phone while if the sensor is located under glass, the sensor is most likely connected by TSVs. Isn’t it really cool, right

Through-Silicon Vias in SiGe BiCMOS and Interposer Technologies for Sub-THz Applications

Im Rahmen der vorliegenden Dissertation zum Thema „Through-Silicon Vias in SiGe BiCMOS and Interposer Technologies for Sub-THz Applications“ wurde auf Basis einer 130 nm SiGe BiCMOS Technologie ein Through-Silicon Via (TSV) Technologiemodul zur Herstellung elektrischer Durchkontaktierungen für die Anwendung im Millimeterwellen und Sub-THz Frequenzbereich entwickelt. TSVs wurden mittels elektromagnetischer Simulationen modelliert und in Bezug auf ihre elektrischen Eigenschaften bis in den sub-THz Bereich bis zu 300 GHz optimiert. Es wurden die Wechselwirkungen zwischen Modellierung, Fertigungstechnologie und den elektrischen Eigenschaften untersucht. Besonderes Augenmerk wurde auf die technologischen Einflussfaktoren gelegt. Daraus schlussfolgernd wurde das TSV Technologiemodul entwickelt und in eine SiGe BiCMOS Technologie integriert. Hierzu wurde eine Via-Middle Integration gewählt, welche eine Freilegung der TSVs von der Wafer Rückseite erfordert. Durch die geringe Waferdicke von ca. 75 μm wird einen Carrier Wafer Handling Prozess verwendet. Dieser Prozess wurde unter der Randbedingung entwickelt, dass eine nachfolgende Bearbeitung der Wafer innerhalb der BiCMOS Pilotlinie erfolgen kann. Die Rückseitenbearbeitung zielt darauf ab, einen Redistribution Layer auf der Rückseite der BiCMOS Wafer zu realisieren. Hierzu wurde ein Prozess entwickelt, um gleichzeitig verschiedene TSV Strukturen mit variablen Geometrien zu realisieren und damit eine hohe TSV Design Flexibilität zu gewährleisten. Die TSV Strukturen wurden von DC bis über 300 GHz charakterisiert und die elektrischen Eigenschaften extrahiert. Dabei wurde gezeigt, dass TSV Verbindungen mit sehr geringer Dämpfung <1 dB bis 300 GHz realisierbar sind und somit ausgezeichnete Hochfrequenzeigenschaften aufweisen. Zuletzt wurden vielfältige Anwendungen wie das Grounding von Hochfrequenzschaltkreisen, Interposer mit Waveguides und 300 GHz Antennen dargestellt. Das Potential für Millimeterwellen Packaging und 3D Integration wurde evaluiert. TSV Technologien sind heutzutage in vielen Anwendungen z.B. im Bereich der Systemintegration von Digitalschaltkreisen und der Spannungsversorgung von integrierten Schaltkreisen etabliert. Im Rahmen dieser Arbeit wurde der Einsatz von TSVs für Millimeterwellen und dem sub-THz Frequenzbereich untersucht und die Anwendung für den sub-THz Bereich bis 300 GHz demonstriert. Dadurch werden neue Möglichkeiten der Systemintegration und des Packaging von Höchstfrequenzsystemen geschaffen.:Bibliographische Beschreibung List of symbols and abbreviations Acknowledgement 1. Introduction 2. FEM Modeling of BiCMOS & Interposer Through-Silicon Vias 3. Fabrication of BiCMOS & Silicon Interposer with TSVs 4. Characterization of BiCMOS Embedded Through-Silicon Vias 5. Applications 6. Conclusion and Future Work 7. Appendix 8. Publications & Patents 9. Bibliography 10. List of Figures and Table