Reliability Analysis of Power Electronic Devices

The thesis deals with the reliability of Power Electronic Devices to the purpose of evaluating the phenomena which mainly dictate the limiting conditions where a power device can safely operate. Reliability analyses are conducted by means of either simulations and experimental measurements

Finite element electrothermal modelling and characterization of single and parallel connected power devices

Power modules typically comprise of several power devices connected in parallel for the purpose of delivering high current capability. This is especially the case in SiC where small active area and low current MOSFETs are the only option due to defect density control and yield issues in the epitaxial growth of SiC wafers. Electrothermal variations between parallel connected devices can emerge from manufacturing variability, non-uniform degradation rates, variation in gate driving just to mention a few. The impact of electrothermal variation between parallel-connected devices as a function of device technology is thus important to consider especially since failure of the power module requires only failure in a single device. Furthermore, the impact of these electrothermal variations in parallel-connected devices on the total electrothermal ruggedness of the power module under anomalous switching conditions like unclamped inductive switching is important to consider for the different device technologies. In this thesis, the impact of initial junction temperature variation, switching rates and thermal boundary conditions between parallel-connected diodes have been evaluated for SiC Schottky and silicon PiN diodes under clamped and unclamped inductive switching. Finite element simulations have been used to support the experimental measurements. Similar studies have been performed in CoolMOS super-junction MOSFETs, silicon IGBTs and SiC power MOSFETs. New insights regarding the failure of parallel connected devices under unclamped inductive switching have been revealed from the models and measurements. Overall, the thesis makes a major contribution in the understanding of the electrothermal performance of parallel connected devices for different transistor and diode technologies

Reliability-Oriented Strategies for Multichip Module Based Mission Critical Industry Applications

The availability is defined as the portion of time the system remains operational to serve its purpose. In mission critical applications (MCA), the availability of power converters are determinant to ensure continue productivity and avoid financial losses. Multichip Modules (MCM) are widely adopted in such applications due to the high power density and reduced price; however, the high number of dies inside a compact package results in critical thermal deviations among them. Moreover, uneven power flow, inhomogeneous cooling and accumulated degradation, potentially result in thermal deviation among modules, thereby increasing the temperature differences and resulting in extra temperature in specific subset of devices. High temperatures influences multiple failure mechanisms in power modules, especially in highly dynamic load profiles. Therefore, the higher failure probability of the hottest dies drastically reduces the reliability of mission critical power converters. Therefore, this work investigate reliability-oriented solutions for the design and thermal management of MCM-based power converters applied in mission critical applications. The first contribution, is the integration of a die-level thermal and probabilistic analysis on the design for reliability (DFR) procedure, whereby the temperature and failure probability of each die are taken into account during the reliability modeling. It is demonstrated that the dielevel analysis can obtain more realistic system-level reliability of MCM-based power converters. Thereafter, three novel die-level thermal balancing strategies, based on a modified MCM - with more gate-emitter connections - are proposed and investigated. It is proven that the temperatures inside the MCM can be overcame, and the maximum temperate reduced in up to 8 %

DEVELOPMENT OF NEMS RELAYS IN LOGIC COMPUTATION AND RUGGED ELECTRONICS

Ph.DDOCTOR OF PHILOSOPH

Etude de l’impact de micro-cavités (voids) dans les attaches de puces des modules électroniques de puissance

Power converters nowadays are required to function under harsh conditions in meeting energy efficiency and reliability requirement. Whereas, industrial specifications tend toward a higher level of power integration in respect to the cost constraint. As a result, the die attach is one of the key elements in power module packaging because of high current densities and high heat flow which are transported through. Void formation in the die attach may lead to performance degradation and premature aging of the component. This study introduces a methodology based on the comparison of numerical simulations and experimental campaigns. The obtained results help to improve our understanding on the electro-thermal behaviour of MOSFETs with solder voids. In this thesis, we depict a finite element model in which electro-thermal coupling of a MOSFET active layer is taken in to account. Simulation results will be correlated to the experimental responses. Later on, a parametric numerical study based on the response surface method (RSM) which minimizes the number of simulations and future tests will be exploited to quantify the impact of void position and size on several selective performance criteria. A future serial experimental study in respect to the same RSM design is expected in prospect, in order to fulfil the complementarity for this approach.Les convertisseurs électroniques de puissance sont voués à fonctionner sous des conditions applicatives de plus en plus sévères tout en respectant les impératifs d’efficacité énergétique et de fiabilité. Or, les besoins industriels tendent vers un plus haut niveau d’intégration fonctionnelle tout en améliorant le rapport qualité-prix. Dès lors, la solution utilisée pour le report des puces semi-conductrices est le siège de densités de courant importantes et d’un flux thermique élevé. La présence de défauts dans cette couche d’interconnexion peut conduire à la dégradation de ses performances et au vieillissement prématuré du composant. L’objectif de nos recherches est d’évaluer la pertinence d’une méthodologie basée sur la confrontation de simulations numériques et de campagnes expérimentales. L’objectif est d’améliorer la compréhension du comportement électrothermique en régime de conduction d’un transistor MOSFET en présence d’un void dans sa brasure. Dans cette manuscrite, nous présenterons la construction d’un modèle intégrant le couplage électrothermique de la partie active qui sera confronté à la réponse de résultats expérimentaux. Puis, une étude numérique basée sur la théorie des plans fractionnaires, qui minimise le nombre de simulations, sera exploitée afin de quantifier l’impact de la taille et de la position du défaut sur la réponse électrothermique du composant et de ses liaisons électriques. Les détails de la mise en place d’une étude expérimentale analogue permettront de mettre en perspective la complémentarité de cette approche

3-D electrothermal simulation of active cycling on smart power MOSFETs during short-circuit and UIS conditions

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