Multichannel 25 Gb/s low-power driver and transimpedance amplifier integrated circuits for 100 Gb/s optical links

Highly integrated electronic driver and receiver ICs with low-power consumption are essential for the development of cost-effective multichannel fiber-optic transceivers with small form factor. This paper presents the latest results of a two-channel 28 Gb/s driver array for optical duobinary modulation and a four-channel 25 Gb/s TIA array suited for both NRZ and optical duobinary detection. This paper demonstrated that 28 Gb/s duobinary signals can be efficiently generated on chip with a delay-and-add digital filter and that the driver power consumption can be significantly reduced by optimizing the drive impedance well above 50 Omega, without degrading the signal quality. To the best of our knowledge, this is the fastest modulator driver with on-chip duobinary encoding and precoding, consuming only 652 mW per channel at a differential output swing of 6 Vpp. The 4 x 25 Gb/s TIA shows a good sensitivity of - 10.3 dBm average optical input power at 25 Gb/s for PRBS 2(31) -1 and low power consumption of 77 mW per channel. Both ICs were developed in a 130 nm SiGe BiCMOS process

올 디지털 클럭 및 데이터 복원 회로를 적용한 고속 광 수신기 설계

학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2016. 8. 정덕균.This thesis presents a 22- to 26.5-Gb/s optical receiver with an all-digital clock and data recovery (ADCDR) fabricated in a 65-nm CMOS process. The receiver consists of an optical front-end and a half-rate bang-bang clock and data recovery circuit. The optical front-end achieves low power consumption by using inverter-based amplifiers and realizes sufficient bandwidth by applying several bandwidth extension techniques. In addition, in order to minimize additional jitter at the front-end, not only magnitude and bandwidth but also phase delay responses are considered. The ADCDR employs an LC quadrature digitally-controlled oscillator (LC-QDCO) to achieve a high phase noise figure-of-merit at tens of gigahertz. The recovered clock jitter is 1.28 psrms and the measured jitter tolerance exceeds the tolerance mask specified in IEEE 802.3ba. The receiver sensitivity is 106 and 184 μApk-pk for a bit error rate of 10−12 at data rates of 25 and 26.5 Gb/s, respectively. The entire receiver chip occupies an active die area of 0.75 mm2 and consumes 254 mW at a data rate of 26.5 Gb/s. The energy efficiencies of the front-end and entire receiver at 26.5 Gb/s are 1.35 and 9.58 pJ/bit, respectively.CHAPTER 1 INTRODUCTION 1 1.1 MOTIVATION 1 1.2 THESIS ORGANIZATION 5 CHAPTER 2 DESIGN OF OPTICAL FRONT-END 7 2.1 OVERVIEW 7 2.2 BACKGROUND ON OPTICAL FRONT-END 9 2.2.1 PHOTODIODE 9 2.2.2 TRANSIMPEDANCE AMPLIFIER 11 2.2.3 POST AMPLIFIER 17 2.2.4 SHUNT INDUCTIVE PEAKING 25 2.3 CIRCUIT IMPLEMENTATION 29 2.3.1 OVERALL ARCHITECTURE 29 2.3.2 TRANSIMPEDANCE AMPLIFIER 31 2.3.3 POST AMPLIFIER 34 2.4 NOISE ANALYSIS 43 2.4.1 PHOTODIODE 43 2.4.2 OPTICAL FRONT-END 44 2.4.3 SENSITIVITY 46 CHAPTER 3 DESIGN OF ADCDR FOR OPTICAL RECEIVER 48 3.1 OVERVIEW 48 3.2 BACKGROUND ON PLL-BASED ADCDR 51 3.2.1 PHASE DETECTOR 51 3.2.2 DIGITAL LOOP FILTER 54 3.2.3 DIGITALLY-CONTROLLED OSCILLATOR 56 3.2.4 ANALYSIS OF BANG-BANG ADCDR 67 3.3 CIRCUIT IMPLEMENTATION 70 3.3.1 OVERALL ARCHITECTURE 70 3.3.2 PHASE DETECTION LOGIC 75 3.3.3 DIGITAL LOOP FILTER 77 3.3.4 LC QUADRATURE DCO 78 CHAPTER 4 EXPERIMENTAL RESULTS 82 CHAPTER 5 CONCLUSION 90 BIBLIOGRAPHY 92 초록 101Docto

A Sub-Centimeter Ranging Precision LIDAR Sensor Prototype Based on ILO-TDC

This thesis introduces a high-resolution light detection and ranging (LIDAR) sensor system-on-a-chip (SoC) that performs sub-centimeter ranging precision and maximally 124-meter ranging distance. With off-chip connected avalanche photodiodes (APDs), the time-of-flight (ToF) are resolved through 31×1 time-correlated single photon counting (TCSPC) channels. Embedded time-to-digital converters (TDCs) support 52-ps time resolution and 14-bit dynamic range. A novel injection-locked oscillator (ILO) based TDC are proposed to minimize the power of fine TDC clock distribution, and improve time precision. The global PVT variation among ILO clock distribution is calibrated by an on-chip phase-looked-loop (PLL) that assures a reliable counting performance over wide operating range. The proposed LIDAR sensor is designed, fabricated, and tested in the 65nm CMOS technology. Whole SoC consumes 37mW and each TDC channel consumes 788μW at nominal operation. The proposed TDC design achieved single-shot precision of 38.5 ps, channel uniformity of 14 ps, and DNL/INL of 0.56/1.56 LSB, respectively. The performance of proposed ILO-TDC makes it an excellent candidate for global counting TCSPC in automotive LIDAR

Modeling of Photonic Devices and Photonic Integrated Circuits for Optical Interconnect and RF Photonic Front-End Applications

Photonic integrated circuits (PICs) offer compelling solutions for applications in many areas due to the sufficient functionality and excellent performance. Optical interconnects and radio frequency (RF) photonics are two areas in which PICs have potential to be widely used. Optical interconnect system efficiency is dependent on the ability to optimize the transceiver circuitry for low-power and high-bandwidth operation, motivating co-simulation environments with compact optical device simulation models. Compact models for vertical-cavity surface-emitting lasers (VCSELs) and silicon carrier-injection/depletion ring modulators which include both non-linear electrical and optical dynamics are presented, and excellent matching between co-simulated and measured optical eye diagrams is achieved. Advanced modulation schemes, such as four-level pulse-amplitude modulation (PAM4), are currently under consideration in both high-speed electrical and optical interconnect systems. How NRZ and PAM4 modulation impacts the energy efficiency of an optical link architecture based on silicon photonic microring resonator modulators and drop filters is analyzed. Two ring modulator device structures are proposed for PAM4 modulation, including a single-segment device driven with a multi-level PAM4 transmitter and a two-segment device driven by two simple NRZ (MSB/LSB) transmitters. Modeling results show that the PAM4 architectures achieve superior energy efficiency at higher data rates due to the relaxed circuit bandwidth. While RF photonics offer the promise of chip-scale opto-electrical systems with high levels of functionality, in order to avoid long and unsuccessful design cycles, efficient models that allow for co-simulation are necessary. In order to address this, an optical element modeling framework is proposed based on Verilog-A which allows for the co-simulation of optical elements with transistor-level circuits in a Cadence design environment. Three components in the RF photonic system, Mach Zehnder (MZ) modulators, 4th order all pass filter (APF)-based optical filters, and jammer-suppression notch filters are presented to demonstrate the capability of efficient system design in co-simulation environments

Design of High-Speed CMOS Interface Circuits for Optical Communications

학위논문 (박사)-- 서울대학교 대학원 공과대학 전기·컴퓨터공학부, 2017. 8. 정덕균.The bandwidth requirement of wireline communications has increased ex-ponentially because of the ever-increasing demand for data centers and high-performance computing systems. However, it becomes difficult to satisfy the requirement with legacy electrical links which suffer from frequency-dependent losses due to skin effect, dielectric loss, channel reflections, and crosstalk, resulting in a severe bandwidth limitation. In order to overcome this challenge, it is necessary to introduce optical communication technology, which has been mainly used for long-reach communications, such as long-haul net-works and metropolitan area networks, to the medium- and short-reach com-munication systems. However, there still remain important issues to be resolved to facilitate the adoption of the optical technologies. The most critical challeng-es are the energy efficiency and the cost competitiveness as compared to the legacy copper-based electrical communications. One possible solution is silicon photonics that has long been investigated by a number of research groups. De-spite inherent incompatibility of silicon with the photonic world, silicon pho-tonics is promising and is the only solution that can leverage the mature CMOS technologies. In this thesis, we summarize the current status of silicon photonics and pro-vide the prospect of the optical interconnection. We also present key circuit techniques essential to the implementation of high-speed and low-power optical receivers. And then, we propose optical receiver architectures satisfying the aforementioned requirements with novel circuit techniques.CHAPTER 1 INTRODUCTION 1 1.1 MOTIVATION 1 1.2 THESIS ORGANIZATION 6 CHAPTER 2 BACKGROUND OF OPTICAL COMMUNICATION 7 2.1 OVERVIEW OF OPTICAL LINK 7 2.2 SILICON PHOTONICS 11 2.3 HYBRID INTEGRATION 22 2.4 SILICON-BASED PHOTODIODES 28 2.4.1 BASIC TERMINOLOGY 28 2.4.2 SILICON PD 29 2.4.3 GERMANIUM PD 32 2.4.4 INTEGRATION WITH WAVEGUIDE 33 CHAPTER 3 CIRCUIT TECHNIQUES FOR OPTICAL RECEIVER 35 3.1 BASIS OF TRANSIMPEDANCE AMPLIFIER 35 3.2 TOPOLOGY OF TIA 39 3.2.1 RESISTOR-BASED TIA 39 3.2.2 COMMON-GATE-BASED TIA 41 3.2.3 FEEDBACK-BASED TIA 44 3.2.4 INVERTER-BASED TIA 47 3.2.5 INTEGRATING RECEIVER 48 3.3 BANDWIDTH EXTENSION TECHNIQUES 49 3.3.1 INDUCTOR-BASED TECHNIQUE 49 3.3.2 EQUALIZATION 61 3.4 CLOCK AND DATA RECOVERY CIRCUITS 66 3.4.1 CDR BASIC 66 3.4.2 CDR EXAMPLES 68 CHAPTER 4 LOW-POWER OPTICAL RECEIVER FRONT-END 73 4.1 OVERVIEW 73 4.2 INVERTER-BASED TIA WITH RESISTIVE FEEDBACK 74 4.3 INVERTER-BASED TIA WITH RESISTIVE AND INDUCTIVE FEEDBACK 81 4.4 CIRCUIT IMPLEMENTATION 89 4.5 MEASUREMENT RESULTS 93 CHAPTER 5 BANDWIDTH- AND POWER-SCALABLE OPTICAL RECEIVER FRONT-END 96 5.1 OVERVIEW 96 5.2 BANDWIDTH AND POWER SCALABILITY 97 5.3 GM STABILIZATION 98 5.4 OVERALL BLOCK DIAGRAM OF RECEIVER 104 5.5 MEASUREMENT RESULTS 111 CHAPTER 6 CONCLUSION 118 BIBLIOGRAPHY 120 초 록 131Docto

Survey of Photonic and Plasmonic Interconnect Technologies for Intra-Datacenter and High-Performance Computing Communications

Large scale data centers (DC) and high performance computing (HPC) systems require more and more computing power at higher energy efficiency. They are already consuming megawatts of power, and a linear extrapolation of trends reveals that they may eventually lead to unrealistic power consumption scenarios in order to satisfy future requirements (e.g., Exascale computing). Conventional complementary metal oxide semiconductor (CMOS)-based electronic interconnects are not expected to keep up with the envisioned future board-to-board and chip-to-chip (within multi-chip-modules) interconnect requirements because of bandwidth-density and power-consumption limitations. However, low-power and high-speed optics-based interconnects are emerging as alternatives for DC and HPC communications; they offer unique opportunities for continued energy-efficiency and bandwidth-density improvements, although cost is a challenge at the shortest length scales. Plasmonics-based interconnects on the other hand, due to their extremely small size, offer another interesting solution for further scaling operational speed and energy efficiency. At the device-level, CMOS compatibility is also an important issue, since ultimately photonics or plasmonics will have to be co-integrated with electronics. In this paper, we survey the available literature and compare the aforementioned interconnect technologies, with respect to their suitability for high-speed and energy-efficient on-chip and offchip communications. This paper refers to relatively short links with potential applications in the following interconnect distance hierarchy: local group of racks, board to board, module to module, chip to chip, and on chip connections. We compare different interconnect device modules, including low-energy output devices (such as lasers, modulators, and LEDs), photodetectors, passive devices (i.e., waveguides and couplers) and electrical circuitry (such as laserdiode drivers, modulator drivers, transimpedance, and limiting amplifiers). We show that photonic technologies have the potential to meet the requirements for selected HPC and DC applications in a shorter term. We also present that plasmonic interconnect modules could offer ultra-compact active areas, leading to high integration bandwidth densities, and low device capacitances allowing for ultra-high bandwidth operation that would satisfy the application requirements further into the future

Transmetteurs photoniques sur silicium pour les transmissions optiques à grande capacité

Les applications exigeant des très nombreuses données (médias sociaux, diffusion vidéo en continu, mégadonnées, etc.) se développent à un rythme rapide, ce qui nécessite de plus en plus de liaisons optiques ultra-rapides. Ceci implique le développment des transmetteurs optiques intégrés et à bas coût et plus particulirement en photonique sur silicium en raison de ses avantages par rapport aux autres technologies (LiNbO3 et InP), tel que la compatibilité avec le procédé de fabrication CMOS. Les modulateurs optoélectronique sont un élément essentiel dans la communication op-tique. Beaucoup de travaux de recherche sont consacrées au développement de dispositifs optiques haut débit efficaces. Cependant, la conception de modulateurs en photonique sur sili-cium (SiP) haut débit est diffcile, principalement en raison de l'absence d'effet électro-optique intrinsèque dans le silicium. De nouvelles approches et de architectures plus performances doivent être développées afin de satisfaire aux critères réliés au système d'une liaison optique aux paramètres de conception au niveau du dispositif integré. En outre, la co-conception de circuits integrés photoniques sur silicium et CMOS est cruciale pour atteindre tout le potentiel de la technologie de photonique sur silicium. Ainsi cette thèse aborde les défits susmentionnés. Dans notre première contribution, nous préesentons pour la première fois un émetteur phononique sur silicium PAM-4 sans utiliser un convertisseur numérique analog (DAC)qui comprend un modulateur Mach Zehnder à électrodes segmentées SiP (LES-MZM) implémenté dans un procédé photonique sur silicium générique avec jonction PN latérale et son conducteur CMOS intégré. Des débits allant jusqu'à 38 Gb/s/chnnel sont obtenus sans utili-ser un convertisseur numérique-analogique externe. Nous présentons également une nouvelle procédure de génération de délai dans le excitateur de MOS complémentaire. Un effet, un délai robuste aussi petit que 7 ps est généré entre les canaux de conduite. Dans notre deuxième contribution, nous présentons pour la première fois un nouveau fac-teur de mérite (FDM) pour les modulateurs SiP qui inclut non seulement la perte optique et l'efficacité (comme les FDMs précédents), mais aussi la bande passante électro-optique du modulateur SiP (BWEO). Ce nouveau FDM peut faire correspondre les paramètres de conception physique du modulateur SiP à ses critères de performance au niveau du système, facilitant à la fois la conception du dispositif optique et l'optimisation du système. Pour la première fois nous définissons et utilisons la pénalité de puissance du modulateur (MPP) induite par le modulateur SiP pour étudier la dégradation des performances au niveau du système induite par le modulateur SiP dans une communication à base de modulation d'amplitude d'impulsion optique. Nous avons développé l'équation pour MPP qui inclut les facteurs de limitation du modulateur (perte optique, taux d'extinction limité et limitation de la bande passante électro-optique). Enfin, dans notre troisième contribution, une nouvelle méthodologie de conception pour les modulateurs en SiP intégré à haute débit est présentée. La nouvelle approche est basée sur la minimisation de la MPP SiP en optimisant l'architecture du modulateur et le point de fonctionnement. Pour ce processus, une conception en longueur unitaire du modulateur Mach Zehnder (MZM) peut être optimisée en suivant les spécifications du procédé de fabrication et les règles de conception. Cependant, la longueur et la tension de biais du d'éphaseur doivent être optimisées ensemble (par exemple selon vitesse de transmission et format de modulation). Pour vérifier l'approche d'optimisation proposée expérimentale mont, a conçu un modulateur photonique sur silicium en phase / quadrature de phase (IQ) ciblant le format de modulation 16-QAM à 60 Gigabaud. Les résultats expérimentaux prouvent la fiabilité de la méthodologie proposée. D'ailleurs, nous avons augmenté la vitesse de transmission jusqu'à 70 Gigabaud pour tester la limite de débit au système. Une transmission de données dos à dos avec des débits binaires de plus de 233 Gigabit/s/channel est observée. Cette méthodologie de conception ouvre ainsi la voie à la conception de la prochaine génération d'émetteurs intégrés à double polarisation 400+ Gigabit/s/channel.Data-hungry applications (social media, video streaming, big data, etc.) are expanding at a fast pace, growing demand for ultra-fast optical links. This driving force reveals need for low-cost, integrated optical transmitters and pushes research in silicon photonics because of its advantages over other platforms (i.e. LiNbO3 and InP), such as compatibility with CMOS fabrication processes, the ability of on-chip polarization manipulation, and cost effciency. Electro-optic modulators are an essential component of optical communication links and immense research is dedicated to developing effcient high-bitrate devices. However, the design of high-capacity Silicon Photonics (SiP) transmitters is challenging, mainly due to lack of inherent electro-optic effect in silicon. New design methodologies and performance merits have to be developed in order to map the system-level criteria of an optical link to the design parameters in device-level. In addition, co-design of silicon photonics and CMOS integrated circuits is crucial to reveal the full potential of silicon photonics. This thesis addresses the aforementioned challenges. In our frst contribution, for the frst time we present a DAC-less PAM-4 silicon photonic transmitter that includes a SiP lumped-element segmented-electrode Mach Zehnder modula-tor (LES-MZM) implemented in a generic silicon photonic process with lateral p-n junction and its co-designed CMOS driver. Using post processing, bitrates up to 38 Gb/s/channel are achieved without using an external digital to analog converter. We also presents a novel delay generation procedure in the CMOS driver. A robust delay as small as 7 ps is generated between the driving channels. In our second contribution, for the frst time we present a new figure of merit (FOM) for SiP modulators that includes not only the optical loss and effciency (like the prior FOMs), but also the SiP modulator electro-optic bandwidth ( BWEO). This new FOM can map SiP modulator physical design parameters to its system-level performance criteria, facilitating both device design and system optimization. For the frst time we define and employ the modulator power penalty (MPP) induced by the SiP modulator to study the system level performance degradation induced by SiP modulator in an optical pulse amplitude modulation link. We develope a closed-form equation for MPP that includes the SiP modulator limiting factors (optical loss, limited extinction ratio and electro-optic bandwidth limitation). Finally in our third contribution, we present a novel design methodology for integrated high capacity SiP modulators. The new approach is based on minimizing the power penalty of a SiP modulator (MPP) by optimizing modulator design and bias point. For the given process, a unit-length design of Mach Zehnder modulator (MZM) can be optimized following the process specifications and design rules. However, the length and the bias voltage of the phase shifter must be optimized together in a system context (e.g., baud rate and modulation format). Moreover, to verify the proposed optimization approach in experiment, we design an in-phase/quadrature-phase (IQ) silicon photonic modulator targeting 16-QAM modulation format at 60 Gbaud. Experimental results proves the reliability of our proposed methodology. We further push the baud rate up to 70 Gbaud to examine the capacity boundary of the device. Back to back data transmission with bitrates more than 233 Gb/s/channel are captured. This design methodology paves the way for designing the next generation of integrated dual- polarization 400+ Gb/s/channel transmitters

Design of Optical Interconnect Transceiver Circuits and Network-on-chip Architectures for Inter- and Intra-chip Communication

The rapid expansion in data communication due to the increased multimedia applications and cloud computing services necessitates improvements in optical transceiver circuitry power efficiency as these systems scale well past 10 Gb/s. In order to meet these requirements, a 26 GHz transimpedance amplifier (TIA) is presented in a 0.25-µm SiGe BiCMOS technology. It employs a transformer-based regulated cascode (RGC) input stage which provides passive negative-feedback gain that enhances the effective transconductance of the TIA’s input common-base transistor; reducing the input resistance and pro- viding considerable bandwidth extension without significant noise degradation or power consumption. The TIA achieves a 53 dBΩ single-ended transimpedance gain with a 26√ GHz bandwidth and 21.3 pA/H z average input-referred noise current spectral density. Total chip power including output buffering is 28.2 mW from a 2.5 V supply, with the core TIA consuming 8.2 mW, and the chip area including pads is 960 µm × 780 µm. With the advance of photonic devices, optical interconnects becomes a promising technology to replace the conventional electrical channels for the high-bandwidth and power efficient inter/intra-chip interconnect. Second, a silicon photonic transceiver is presented for a silicon ring resonator-based optical interconnect architecture in a 1V standard 65nm CMOS technology. The transmitter circuits incorporate high-swing drivers with non-linear pre-emphasis and automatic bias-based tuning for resonance wavelength stabilization. An optical forwarded-clock adaptive inverter-based transimpedance amplifier (TIA) receiver trades-off power for varying link budgets by employing an on-die eye monitor and scaling the TIA supply for the required sensitivity. At 5 GB/s operation, the ring modulator un- der 4Vpp driver achieves 12.7dB extinction ratio with 4.04mW power consumption, while a 0.28nm tuning range is obtained at 6.8µW/GHz efficiency with the bias-based tuning scheme implemented with the 2Vpp transmitter. When tested with a wire-bonded 150f- F p-i-n photodetector, the receiver achieves -12.7dBm sensitivity at a BER=10−15 and consumes 2.2mW at 8 GB/s. Third, a novel Nano-Photonic Network-on-Chip (NoC) architecture, called LumiNoC, is proposed for high performance and power-efficient interconnects for the chip-multi- processors (CMPs). A 64-node LumiNoC under synthetic traffic enjoys 50% less latency at low loads versus other reported photonic NoCs, and ∼25% less latency versus the electrical 2D mesh NoCs on realistic workloads. Under the same ideal throughput, LumiNoC achieves laser power reduction of 78%, and overall power reduction of 44% versus competing designs

Modeling and Design of High-Speed CMOS Receivers for Short-Reach Photonic Links

This dissertation presents several research outcomes towards designing high-speed CMOS optical receivers for energy-efficient short-reach optical links. First, it provides a wide survey of recently published equalizer-based receivers and presents a novel methodology to accurately calculate their noise. The proposed methodology is then used to find the receiver that achieves the best sensitivity. Second, the trade-off between sensitivity and power dissipation of the receiver is optimized to reduce the energy consumption per bit of the overall link. Design trade-offs for the receiver, transmitter, and the overall link are presented, and comparisons are made to study how much receiver sensitivity can be sacrificed to save its power dissipation before this power reduction is outpaced by the transmitter’s increase in power. Unlike conventional wisdom, our results show that energy-efficient links require low-power receivers with input capacitance much smaller than that required for noise-optimum performance. Third, the thesis presents a novel equalization technique for optical receivers. A linear equalizer (LE) is realized by adding a pole in the feedback paths of an active feedback-based wideband amplifier. By embedding the peaking in the main amplifier (MA), the front-end meets the sensitivity and gain of conventional LE-based receivers with better energy efficiency by eliminating the standalone equalizer stage(s). Electrical measurements are presented to demonstrate the capability of the proposed technique in restoring the bandwidth and improving the performance over the conventional design