Designing a Ring Oscillator Using Nanotechnology through Cadence Virtuoso

This paper presents the design and simulation of a ring oscillator using nanotechnology and the Cadence Virtuoso platform. As feature sizes continue to shrink, new design methodologies are required to account for quantum effects that become prominent at the nanoscale. This paper utilizes predictive technology models for a 45nm process to design a three-stage ring oscillator with minimum channel lengths. The ring oscillator design is optimized through careful selection of transistor characteristics and layout considerations. Post-layout simulations demonstrate functionality with oscillation frequency and phase noise matching expected theoretical values. The completed design provides a demonstration of a basic analog circuit block implemented with nanoscale technology. &nbsp

Asymmetric 5.5 GHz Three-Stage Voltage-Controlled Ring-Oscillator in 65 nm CMOS Technology

The current trend of increasing the complexity of hardware accelerators to improve their functionality is highlighting the problem of sharing a high-frequency clock signal for all integrated modules. As the clock itself is becoming the main limitation to the performance of accelerators, in this manuscript, we present the design of an asymmetric Ring Oscillator-Voltage-Controlled Oscillator (RO-VCO) based on the Current Mode Logic architecture. The RO-VCO was designed on commercial-grade 65 nm CMOS technology, and it is capable of driving large capacitance loads, avoiding the need for additional buffers for clock-trees, reducing the silicon area and power consumption. The proposed RO-VCO is composed of three closed-loop differential and asymmetrical stages, and it is able to tune the working frequency in the range from 4.72 GHz to 6.12 GHz. The phase noise and a figure of merit of −103.2 dBc/Hz and −186 dBc/Hz were obtained at 1 MHz offset from the 5.5 GHz carrier. In this article, the analytical model, full custom schematic, and layout of the proposed RO-VCO are presented and discussed in detail together with the experimental electrical and thermal characterization of the fabricated device

Design and Analysis of a True Random Number Generator Based on GSR Signals for Body Sensor Networks

This article belongs to the Section Internet of ThingsToday, medical equipment or general-purpose devices such as smart-watches or smart-textiles can acquire a person's vital signs. Regardless of the type of device and its purpose, they are all equipped with one or more sensors and often have wireless connectivity. Due to the transmission of sensitive data through the insecure radio channel and the need to ensure exclusive access to authorised entities, security mechanisms and cryptographic primitives must be incorporated onboard these devices. Random number generators are one such necessary cryptographic primitive. Motivated by this, we propose a True Random Number Generator (TRNG) that makes use of the GSR signal measured by a sensor on the body. After an exhaustive analysis of both the entropy source and the randomness of the output, we can conclude that the output generated by the proposed TRNG behaves as that produced by a random variable. Besides, and in comparison with the previous proposals, the performance offered is much higher than that of the earlier works.This work was supported by the Spanish Ministry of Economy and Competitiveness under the contract ESP-2015-68245-C4-1-P, by the MINECO grant TIN2016-79095-C2-2-R (SMOG-DEV), and by the Comunidad de Madrid (Spain) under the project CYNAMON (P2018/TCS-4566), co-financed by European Structural Funds (ESF and FEDER). This research was also supported by the Interdisciplinary Research Funds (HTC, United Arab Emirates) under the grant No. 103104

Low Power Circuits for Smart Flexible ECG Sensors

Cardiovascular diseases (CVDs) are the world leading cause of death. In-home heart condition monitoring effectively reduced the CVD patient hospitalization rate. Flexible electrocardiogram (ECG) sensor provides an affordable, convenient and comfortable in-home monitoring solution. The three critical building blocks of the ECG sensor i.e., analog frontend (AFE), QRS detector, and cardiac arrhythmia classifier (CAC), are studied in this research. A fully differential difference amplifier (FDDA) based AFE that employs DC-coupled input stage increases the input impedance and improves CMRR. A parasitic capacitor reuse technique is proposed to improve the noise/area efficiency and CMRR. An on-body DC bias scheme is introduced to deal with the input DC offset. Implemented in 0.35m CMOS process with an area of 0.405mm2, the proposed AFE consumes 0.9W at 1.8V and shows excellent noise effective factor of 2.55, and CMRR of 76dB. Experiment shows the proposed AFE not only picks up clean ECG signal with electrodes placed as close as 2cm under both resting and walking conditions, but also obtains the distinct -wave after eye blink from EEG recording. A personalized QRS detection algorithm is proposed to achieve an average positive prediction rate of 99.39% and sensitivity rate of 99.21%. The user-specific template avoids the complicate models and parameters used in existing algorithms while covers most situations for practical applications. The detection is based on the comparison of the correlation coefficient of the user-specific template with the ECG segment under detection. The proposed one-target clustering reduced the required loops. A continuous-in-time discrete-in-amplitude (CTDA) artificial neural network (ANN) based CAC is proposed for the smart ECG sensor. The proposed CAC achieves over 98% classification accuracy for 4 types of beats defined by AAMI (Association for the Advancement of Medical Instrumentation). The CTDA scheme significantly reduces the input sample numbers and simplifies the sample representation to one bit. Thus, the number of arithmetic operations and the ANN structure are greatly simplified. The proposed CAC is verified by FPGA and implemented in 0.18m CMOS process. Simulation results show it can operate at clock frequencies from 10KHz to 50MHz. Average power for the patient with 75bpm heart rate is 13.34W

Integrated Circuits and Systems for Smart Sensory Applications

Connected intelligent sensing reshapes our society by empowering people with increasing new ways of mutual interactions. As integration technologies keep their scaling roadmap, the horizon of sensory applications is rapidly widening, thanks to myriad light-weight low-power or, in same cases even self-powered, smart devices with high-connectivity capabilities. CMOS integrated circuits technology is the best candidate to supply the required smartness and to pioneer these emerging sensory systems. As a result, new challenges are arising around the design of these integrated circuits and systems for sensory applications in terms of low-power edge computing, power management strategies, low-range wireless communications, integration with sensing devices. In this Special Issue recent advances in application-specific integrated circuits (ASIC) and systems for smart sensory applications in the following five emerging topics: (I) dedicated short-range communications transceivers; (II) digital smart sensors, (III) implantable neural interfaces, (IV) Power Management Strategies in wireless sensor nodes and (V) neuromorphic hardware

Circuits and Systems Advances in Near Threshold Computing

Modern society is witnessing a sea change in ubiquitous computing, in which people have embraced computing systems as an indispensable part of day-to-day existence. Computation, storage, and communication abilities of smartphones, for example, have undergone monumental changes over the past decade. However, global emphasis on creating and sustaining green environments is leading to a rapid and ongoing proliferation of edge computing systems and applications. As a broad spectrum of healthcare, home, and transport applications shift to the edge of the network, near-threshold computing (NTC) is emerging as one of the promising low-power computing platforms. An NTC device sets its supply voltage close to its threshold voltage, dramatically reducing the energy consumption. Despite showing substantial promise in terms of energy efficiency, NTC is yet to see widescale commercial adoption. This is because circuits and systems operating with NTC suffer from several problems, including increased sensitivity to process variation, reliability problems, performance degradation, and security vulnerabilities, to name a few. To realize its potential, we need designs, techniques, and solutions to overcome these challenges associated with NTC circuits and systems. The readers of this book will be able to familiarize themselves with recent advances in electronics systems, focusing on near-threshold computing

Advanced CMOS Integrated Circuit Design and Application

The recent development of various application systems and platforms, such as 5G, B5G, 6G, and IoT, is based on the advancement of CMOS integrated circuit (IC) technology that enables them to implement high-performance chipsets. In addition to development in the traditional fields of analog and digital integrated circuits, the development of CMOS IC design and application in high-power and high-frequency operations, which was previously thought to be possible only with compound semiconductor technology, is a core technology that drives rapid industrial development. This book aims to highlight advances in all aspects of CMOS integrated circuit design and applications without discriminating between different operating frequencies, output powers, and the analog/digital domains. Specific topics in the book include: Next-generation CMOS circuit design and application; CMOS RF/microwave/millimeter-wave/terahertz-wave integrated circuits and systems; CMOS integrated circuits specially used for wireless or wired systems and applications such as converters, sensors, interfaces, frequency synthesizers/generators/rectifiers, and so on; Algorithm and signal-processing methods to improve the performance of CMOS circuits and systems

Integrated photonics for millimetre wave transmitters and receivers

This PhD thesis entitled “Integrated photonics for millimetre wave transmitters and receivers” aimed at investigating the possibility of employing the uni-traveling carrier photodiode (UTC-PD) in millimetre wave (MMW) wireless receivers and, eventually, demonstrating a photonic integrated transceiver, by exploiting the concept of optically-pumped mixing (OPM). Previously, the UTC-PD has been successfully demonstrated as an OPM, by mixing an optically-generated local oscillator (LO) with a high frequency RF signal to generate a replica of the RF signal at a low intermediate frequency (IF), defined by the difference between the LO and the RF signal. This concept forms the foundation of this PhD thesis. The principal idea is to deploy the UTC-PD mixer in MMW wireless receivers to down-convert the high frequency data signal into a low frequency IF, where it can be easily processed and recovered. The main challenge to this approach is the low conversion efficiency of the UTC-PD mixer. For example, a conversion loss of 32 dB has been reported at 100 GHz. Also, the detection bandwidth in previous demonstrations was very narrow (around 100 Hz), which is too narrow to be useful in high-speed data communications. Consequently, a significant effort was made, in this thesis, to improve these parameters before the implementation in wireless receivers. The characterization and optimization works done in this thesis on the input parameters to the UTC-PD mixer have advanced the state of the art significantly. For example, conversion losses as low as 22 dB have been reported here. Also, the detection bandwidth has been increased to up to 10 GHz, allowing for multi-Gbps communication links. Based on these promising results, proof of concept wireless data transmission experiments were successfully conducted at different carrier frequencies (33 GHz, 35 GHz, and 60 GHz) using separate non-integrated UTC-PDs at the receiver with speeds of up to 5 Gbps. To the best of the author’s knowledge, this is the first demonstration of the UTC-PD at the receiver. Upon these successful demonstrations, further research was done on a photonic integrated circuit, which comprises UTC-PDs, lasers, optical amplifiers and modulators. The outcome of this research was the first demonstration of a photonic integrated transceiver. This transceiver is suitable for short distance communications and could find interesting applications in 5G and future networks, including: high definition (HD) video streaming, file transfer, and wireless backhaul

Light-Addressing and Chemical Imaging Technologies for Electrochemical Sensing

Visualizing chemical components in a specimen is an essential technology in many branches of science and practical applications. This book deals with electrochemical imaging techniques based on semiconductor devices with capability of spatially resolved sensing. Two types of such sensing devices have been extensively studied and applied in various fields, i.e., arrayed sensors and light-addressed sensors. An ion-sensitive field-effect transistor (ISFET) array and a charge-coupled device (CCD) ion image sensor are examples of arrayed sensors. They take advantage of semiconductor microfabrication technology to integrate a large number of sensing elements on a single chip, each representing a pixel to form a chemical image. A light-addressable potentiometric sensor (LAPS), on the other hand, has no pixel structure. A chemical image is obtained by raster-scanning the sensor plate with a light beam, which can flexibly define the position and size of a pixel. This light-addressing approach is further applied in other LAPS-inspired methods. Scanning photo-induced impedance microscopy (SPIM) realized impedance mapping and light-addressable electrodes/light-activated electrochemistry (LAE) realized local activation of Faradaic processes. This book includes eight articles on state-of-the-art technologies of light-addressing/chemical imaging devices and their application to biology and materials science