High-Speed Low-Power Analog to Digital Converter for Digital Beam Forming Systems

abstract: Time-interleaved analog to digital converters (ADCs) have become critical components in high-speed communication systems. Consumers demands for smaller size, more bandwidth and more features from their communication systems have driven the market to use modern complementary metal-oxide-semiconductor (CMOS) technologies with shorter channel-length transistors and hence a more compact design. Downscaling the supply voltage which is required in submicron technologies benefits digital circuits in terms of power and area. Designing accurate analog circuits, however becomes more challenging due to the less headroom. One way to overcome this problem is to use calibration to compensate for the loss of accuracy in analog circuits. Time-interleaving increases the effective data conversion rate in ADCs while keeping the circuit requirements the same. However, this technique needs special considerations as other design issues associated with using parallel identical channels emerge. The first and the most important is the practical issue of timing mismatch between channels, also called sample-time error, which can directly affect the performance of the ADC. Many techniques have been developed to tackle this issue both in analog and digital domains. Most of these techniques have high complexities especially when the number of channels exceeds 2 and some of them are only valid when input signal is a single tone sinusoidal which limits the application. This dissertation proposes a sample-time error calibration technique which bests the previous techniques in terms of simplicity, and also could be used with arbitrary input signals. A 12-bit 650 MSPS pipeline ADC with 1.5 GHz analog bandwidth for digital beam forming systems is designed in IBM 8HP BiCMOS 130 nm technology. A front-end sample-and-hold amplifier (SHA) was also designed to compare with an SHA-less design in terms of performance, power and area. Simulation results show that the proposed technique is able to improve the SNDR by 20 dB for a mismatch of 50% of the sampling period and up to 29 dB at 37% of the Nyquist frequency. The designed ADC consumes 122 mW in each channel and the clock generation circuit consumes 142 mW. The ADC achieves 68.4 dB SNDR for an input of 61 MHz.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201

Concepts for smart AD and DA converters

This thesis studies the `smart' concept for application to analog-to-digital and digital-to-analog converters. The smart concept aims at improving performance - in a wide sense - of AD/DA converters by adding on-chip intelligence to extract imperfections and to correct for them. As the smart concept can correct for certain imperfections, it can also enable the use of more efficient architectures, thus yielding an additional performance boost. Chapter 2 studies trends and expectations in converter design with respect to applications, circuit design and technology evolution. Problems and opportunities are identfied, and an overview of performance criteria is given. Chapter 3 introduces the smart concept that takes advantage of the expected opportunities (described in chapter 2) in order to solve the anticipated problems. Chapter 4 applies the smart concept to digital-to-analog converters. In the discussed example, the concept is applied to reduce the area of the analog core of a current-steering DAC. It is shown that a sub-binary variable-radix approach reduces the area of the current-source elements substantially (10x compared to state-of-the-art), while maintaining accuracy by a self-measurement and digital pre-correction scheme. Chapter 5 describes the chip implementation of the sub-binary variable-radix DAC and discusses the experimental results. The results confirm that the sub-binary variable-radix design can achieve the smallest published current-source-array area for the given accuracy (12bit). Chapter 6 applies the smart concept to analog-to-digital converters, with as main goal the improvement of the overall performance in terms of a widely used figure-of-merit. Open-loop circuitry and time interleaving are shown to be key to achieve high-speed low-power solutions. It is suggested to apply a smart approach to reduce the effect of the imperfections, unintentionally caused by these key factors. On high-level, a global picture of the smart solution is proposed that can solve the problems while still maintaining power-efficiency. Chapter 7 deals with the design of a 500MSps open-loop track-and-hold circuit. This circuit is used as a test case to demonstrate the proposed smart approaches. Experimental results are presented and compared against prior art. Though there are several limitations in the design and the measurement setup, the measured performance is comparable to existing state-of-the-art. Chapter 8 introduces the first calibration method that counteracts the accuracy issues of the open-loop track-and-hold. A description of the method is given, and the implementation of the detection algorithm and correction circuitry is discussed. The chapter concludes with experimental measurement results. Chapter 9 introduces the second calibration method that targets the accuracy issues of time-interleaved circuits, in this case a 2-channel version of the implemented track-and-hold. The detection method, processing algorithm and correction circuitry are analyzed and their implementation is explained. Experimental results verify the usefulness of the method

Low-power 6-bit 1-GS/s two-channel pipeline ADC with open-loop amplification using amplifiers with local-feedback

IEEE International Symposium on Circuits and Systems, pp. 2258 – 2261, Seattle, EUAA low-power 1.2 V 6-bit 1-GS/s time-interleaved pipeline ADC designed in 130 nm CMOS is described. It is based on a new 2-channel 1.5-bit MDAC that performs openloop residue amplification using a shared amplifier employing local-feedback. Time mismatches between channels are highly attenuated, simply by using two passive front-end Sample-and-Hold circuits, with dedicated switch-linearization control circuits, driven by a single clock phase. Simulated results of the ADC achieve 5.35-bit ENOB, with 20 mW and without requiring any gain control/calibration scheme

Low power VCO-based analog-to-digital conversion

textThis dissertation presents novel two stage ADC architecture with a VCO based second stage. With the scaling of the supply voltages in modern CMOS process it is difficult to design high gain operational amplifiers needed for traditional voltage domain two-stage analog to digital converters. However time resolution continues to improve with the advancement in CMOS technology making VCO-based ADC more attractive. The nonlinearity in voltage-to-frequency transfer function is the biggest challenge in design of VCO based ADC. The hybrid approach used in this work uses a voltage domain first stage to determine the most significant bits and uses a VCO based second stage to quantize the small residue obtained from first stage. The architecture relaxes the gain requirement on the the first stage opamp and also relaxes the linearity requirements on the second stage VCO. The prototype ADC built in 65nm CMOS process achieves 63.7dB SNDR in 10MHz bandwidth while only consuming 1.1mW of power. The performance of the prototype chip is comparable to the state-of-art in terms of figure-of-merit but this new architecture uses significantly less circuit area.Electrical and Computer Engineerin

Design of Low Power and Power Scalable Pipelined ADC Using Current Modulated Power Scale

This work represents a power scalable pipelined ADC, which achieves low power variation depends upon the sampling rate and enables variation in throughput. The keys to power scalability at high sampling rates were current modulation-based architecture and the development of novel rapid power-on Op-amp, which can completely and quickly power on/off by the feedback approach. The result achieved in this design is as high as 50 Msps and as low as 1 ksps, keeping some important parameters of ADC as ENOB and SNDR are almost constant. Power variation in ADC has a flexible range from 7.5 µW to 17 mW, which is lower power consumption than previous works

Parametric analog signal amplification applied to nanoscale cmos wireless digital transceivers

Thesis presented in partial fulfillment of the requirements for the degree of Doctor of Philosophy in the subject of Electrical and Computer Engineering by the Universidade Nova de Lisboa,Faculdade de Ciências e TecnologiaSignal amplification is required in almost every analog electronic system. However noise is also present, thus imposing limits to the overall circuit performance, e.g., on the sensitivity of the radio transceiver. This drawback has triggered a major research on the field, which has been producing several solutions to achieve amplification with minimum added noise. During the Fifties, an interesting out of mainstream path was followed which was based on variable reactance instead of resistance based amplifiers. The principle of these parametric circuits permits to achieve low noise amplifiers since the controlled variations of pure reactance elements is intrinsically noiseless. The amplification is based on a mixing effect which enables energy transfer from an AC pump source to other related signal frequencies. While the first implementations of these type of amplifiers were already available at that time, the discrete-time version only became visible more recently. This discrete-time version is a promising technique since it is well adapted to the mainstream nanoscale CMOS technology. The technique itself is based on the principle of changing the surface potential of the MOS device while maintaining the transistor gate in a floating state. In order words, the voltage amplification is achieved by changing the capacitance value while maintaining the total charge unchanged during an amplification phase. Since a parametric amplifier is not intrinsically dependent on the transconductance of the MOS transistor, it does not directly suffer from the intrinsic transconductance MOS gain issues verified in nanoscale MOS technologies. As a consequence, open-loop and opamp free structures can further emerge with this additional contribution. This thesis is dedicated to the analysis of parametric amplification with special emphasis on the MOS discrete-time implementation. The use of the latter is supported on the presentation of several circuits where the MOS Parametric Amplifier cell is well suited: small gain amplifier, comparator, discrete-time mixer and filter, and ADC. Relatively to the latter, a high speed time-interleaved pipeline ADC prototype is implemented in a,standard 130 nm CMOS digital technology from United Microelectronics Corporation (UMC). The ADC is fully based on parametric MOS amplification which means that one could achieve a compact and MOS-only implementation. Furthermore, any high speed opamp has not been used in the signal path, being all the amplification steps implemented with open-loop parametric MOS amplifiers. To the author’s knowledge, this is first reported pipeline ADC that extensively used the parametric amplification concept.Fundação para a Ciência e Tecnologia through the projects SPEED, LEADER and IMPAC

A 1.67 pJ/Conversion-step 8-bit SAR-Flash ADC Architecture in 90-nm CMOS Technology

A novice advanced architecture of 8-bit analog todigital converter is introduced and analyzed in this work. Thestructure of proposed ADC is based on the sub-ranging ADCarchitecture in which a 4-bit resolution flash-ADC is utilized. Theproposed ADC architecture is designed by employing a comparatorwhich is equipped with common mode current feedback andgain boosting technique (CMFD-GB) and a residue amplifier. Theproposed 8 bits ADC structure can achieve the speed of 140 megasamplesper second. The proposed ADC architecture is designedat a resolution of 8 bits at 10 MHz sampling frequency. DNL andINL values of the proposed design are -0.94/1.22 and -1.19/1.19respectively. The ADC design dissipates a power of 1.24 mWwith the conversion speed of 0.98 ns. The magnitude of SFDRand SNR from the simulations at Nyquist input is 39.77 and 35.62decibel respectively. Simulations are performed on a SPICE basedtool in 90 nm CMOS technology. The comparison shows betterperformance for the proposed ADC design in comparison toother ADC architectures regarding speed, resolution and powerconsumption

Novel techniques for the design and practical realization of switched-capacitor circuits in deep-submicron CMOS technologies

Dissertação apresentada para obtenção do Grau de Doutor em Engenharia Electrotécnica e de Computadores pela Universidade Nova de Lisboa, Faculdade de Ciências e TecnologiaSwitches presenting high linearity are more and more required in switched-capacitor circuits,namely in 12 to 16 bits resolution analog-to-digital converters. The CMOS technology evolves continuously towards lower supply voltages and, simultaneously, new design techniques are necessary to fulfill the realization of switches exhibiting a high dynamic range and a distortion compatible with referred resolutions. Moreover, with the continuously downing of the sizes, the physic constraints of the technology must be considered to avoid the excessive stress of the devices when relatively high voltages are applied to the gates. New switch-linearization techniques, with high reliability, must be necessarily developed and demonstrated in CMOS integrated circuits. Also, the research of new structures of circuits with switched-capacitor is permanent. Simplified and efficient structures are mandatory, adequate to the new demands emerging from the proliferation of portable equipments, necessarily with low energy consumption while assuring high performance and multiple functions. The work reported in this Thesis comprises these two areas. The behavior of the switches under these new constraints is analyzed, being a new and original solution proposed, in order to maintain the performance. Also, proposals for the application of simpler clock and control schemes are presented, and for the use of open-loop structures and amplifiers with localfeedback. The results, obtained in laboratory or by simulation, assess the feasibility of the presented proposals

Design of a low power switched-capacitor pipeline analog-to-digital converter

An Analog to Digital Converter (ADC) is a circuit which converts an analog signal into digital signal. Real world is analog, and the data processed by the computer or by other signal processing systems is digital. Therefore, the need for ADCs is obvious. In this thesis, several novel designs used to improve ADCs operation speed and reduce ADC power consumption are proposed. First, a high speed switched source follower (SSF) sample and hold amplifier without feedthrough penalty is implemented and simulated. The SSF sample and hold amplifier can achieve 6 Bit resolution with sampling rate at 10Gs/s. Second, a novel rail-to-rail time domain comparator used in successive approximation register ADC (SAR ADC) is implemented and simulated. The simulation results show that the proposed SAR ADC can only consume 1.3 muW with a 0.7 V power supply. Finally, a prototype pipeline ADC is implemented and fabricated in an IBM 90nm CMOS process. The proposed design is validated using measurement on a fabricated silicon IC, and the proposed 10-bit ADC achieves a peak signal-to-noise- and-distortion-ratio (SNDR) of 47 dB. This SNDR translates to a figure of merit (FOM) of 2.6N/conversion-step with a 1.2 V power supply

A Low-Power, Reconfigurable, Pipelined ADC with Automatic Adaptation for Implantable Bioimpedance Applications

Biomedical monitoring systems that observe various physiological parameters or electrochemical reactions typically cannot expect signals with fixed amplitude or frequency as signal properties can vary greatly even among similar biosignals. Furthermore, advancements in biomedical research have resulted in more elaborate biosignal monitoring schemes which allow the continuous acquisition of important patient information. Conventional ADCs with a fixed resolution and sampling rate are not able to adapt to signals with a wide range of variation. As a result, reconfigurable analog-to-digital converters (ADC) have become increasingly more attractive for implantable biosensor systems. These converters are able to change their operable resolution, sampling rate, or both in order convert changing signals with increased power efficiency. Traditionally, biomedical sensing applications were limited to low frequencies. Therefore, much of the research on ADCs for biomedical applications focused on minimizing power consumption with smaller bias currents resulting in low sampling rates. However, recently bioimpedance monitoring has become more popular because of its healthcare possibilities. Bioimpedance monitoring involves injecting an AC current into a biosample and measuring the corresponding voltage drop. The frequency of the injected current greatly affects the amplitude and phase of the voltage drop as biological tissue is comprised of resistive and capacitive elements. For this reason, a full spectrum of measurements from 100 Hz to 10-100 MHz is required to gain a full understanding of the impedance. For this type of implantable biomedical application, the typical low power, low sampling rate analog-to-digital converter is insufficient. A different optimization of power and performance must be achieved. Since SAR ADC power consumption scales heavily with sampling rate, the converters that sample fast enough to be attractive for bioimpedance monitoring do not have a figure-of-merit that is comparable to the slower converters. Therefore, an auto-adapting, reconfigurable pipelined analog-to-digital converter is proposed. The converter can operate with either 8 or 10 bits of resolution and with a sampling rate of 0.1 or 20 MS/s. Additionally, the resolution and sampling rate are automatically determined by the converter itself based on the input signal. This way, power efficiency is increased for input signals of varying frequency and amplitude