Continuous-time low-pass filters for integrated wideband radio receivers

This thesis concentrates on the design and implementation of analog baseband continuous-time low-pass filters for integrated wideband radio receivers. A total of five experimental analog baseband low-pass filter circuits were designed and implemented as a part of five single-chip radio receivers in this work. After the motivation for the research work presented in this thesis has been introduced, an overview of analog baseband filters in radio receivers is given first. In addition, a review of the three receiver architectures and the three wireless applications that are adopted in the experimental work of this thesis is presented. The relationship between the integrator non-idealities and integrator Q-factor, as well as the effect of the integrator Q-factor on the filter frequency response, are thoroughly studied on the basis of a literature review. The theoretical study that is provided is essential for the gm-C filter synthesis with non-ideal lossy integrators that is presented after the introduction of different techniques to realize integrator-based continuous-time low-pass filters. The filter design approach proposed for gm-C filters is original work and one of the main points in this thesis, in addition to the experimental IC implementations. Two evolution versions of fourth-order 10-MHz opamp-RC low-pass filters designed and implemented for two multicarrier WCDMA base-station receivers in a 0.25-µm SiGe BiCMOS technology are presented, along with the experimental results of both the low-pass filters and the corresponding radio receivers. The circuit techniques that were used in the three gm-C filter implementations of this work are described and a common-mode induced even-order distortion in a pseudo-differential filter is analyzed. Two evolution versions of fifth-order 240-MHz gm-C low-pass filters that were designed and implemented for two single-chip WiMedia UWB direct-conversion receivers in a standard 0.13-µm and 65-nm CMOS technology, respectively, are presented, along with the experimental results of both the low-pass filters and the second receiver version. The second UWB filter design was also embedded with an ADC into the baseband of a 60-GHz 65-nm CMOS radio receiver. In addition, a third-order 1-GHz gm-C low-pass filter was designed, rather as a test structure, for the same receiver. The experimental results of the receiver and the third gm-C filter implementation are presented

Reconfigurable Receiver Front-Ends for Advanced Telecommunication Technologies

The exponential growth of converging technologies, including augmented reality, autonomous vehicles, machine-to-machine and machine-to-human interactions, biomedical and environmental sensory systems, and artificial intelligence, is driving the need for robust infrastructural systems capable of handling vast data volumes between end users and service providers. This demand has prompted a significant evolution in wireless communication, with 5G and subsequent generations requiring exponentially improved spectral and energy efficiency compared to their predecessors. Achieving this entails intricate strategies such as advanced digital modulations, broader channel bandwidths, complex spectrum sharing, and carrier aggregation scenarios. A particularly challenging aspect arises in the form of non-contiguous aggregation of up to six carrier components across the frequency range 1 (FR1). This necessitates receiver front-ends to effectively reject out-of-band (OOB) interferences while maintaining high-performance in-band (IB) operation. Reconfigurability becomes pivotal in such dynamic environments, where frequency resource allocation, signal strength, and interference levels continuously change. Software-defined radios (SDRs) and cognitive radios (CRs) emerge as solutions, with direct RF-sampling receivers offering a suitable architecture in which the frequency translation is entirely performed in digital domain to avoid analog mixing issues. Moreover, direct RF- sampling receivers facilitate spectrum observation, which is crucial to identify free zones, and detect interferences. Acoustic and distributed filters offer impressive dynamic range and sharp roll off characteristics, but their bulkiness and lack of electronic adjustment capabilities limit their practicality. Active filters, on the other hand, present opportunities for integration in advanced CMOS technology, addressing size constraints and providing versatile programmability. However, concerns about power consumption, noise generation, and linearity in active filters require careful consideration.This thesis primarily focuses on the design and implementation of a low-voltage, low-power RFFE tailored for direct sampling receivers in 5G FR1 applications. The RFFE consists of a balun low-noise amplifier (LNA), a Q-enhanced filter, and a programmable gain amplifier (PGA). The balun-LNA employs noise cancellation, current reuse, and gm boosting for wideband gain and input impedance matching. Leveraging FD-SOI technology allows for programmable gain and linearity via body biasing. The LNA's operational state ranges between high-performance and high-tolerance modes, which are apt for sensitivityand blocking tests, respectively. The Q-enhanced filter adopts noise-cancelling, current-reuse, and programmable Gm-cells to realize a fourth-order response using two resonators. The fourth-order filter response is achieved by subtracting the individual response of these resonators. Compared to cascaded and magnetically coupled fourth-order filters, this technique maintains the large dynamic range of second-order resonators. Fabricated in 22-nm FD-SOI technology, the RFFE achieves 1%-40% fractional bandwidth (FBW) adjustability from 1.7 GHz to 6.4 GHz, 4.6 dB noise figure (NF) and an OOB third-order intermodulation intercept point (IIP3) of 22 dBm. Furthermore, concerning the implementation uncertainties and potential variations of temperature and supply voltage, design margins have been considered and a hybrid calibration scheme is introduced. A combination of on-chip and off-chip calibration based on noise response is employed to effectively adjust the quality factors, Gm-cells, and resonance frequencies, ensuring desired bandpass response. To optimize and accelerate the calibration process, a reinforcement learning (RL) agent is used.Anticipating future trends, the concept of the Q-enhanced filter extends to a multiple-mode filter for 6G upper mid-band applications. Covering the frequency range from 8 to 20 GHz, this RFFE can be configured as a fourth-order dual-band filter, two bandpass filters (BPFs) with an OOB notch, or a BPF with an IB notch. In cognitive radios, the filter’s transmission zeros can be positioned with respect to the carrier frequencies of interfering signals to yield over 50 dB blocker rejection

Broadband RF Front-End Design for Multi-Standard Receiver with High-Linearity and Low-Noise Techniques

Future wireless communication devices must support multiple standards and features on a single-chip. The trend towards software-defined radio requires flexible and efficient RF building blocks which justifies the adoption of broadband receiver front-ends in modern and future communication systems. The broadband receiver front-end significantly reduces cost, area, pins, and power, and can process several signal channels simultaneously. This research is mainly focused on the analysis and realization of the broadband receiver architecture and its various building blocks (LNA, Active Balun-LNA, Mixer, and trans-impedance amplifier) for multi-standard applications. In the design of the mobile DTV tuner, a direct-conversion receiver architecture is adopted achieving low power, low cost, and high dynamic-range for DVB-H standard. The tuner integrates a single-ended RF variable gain amplifier (RFVGA), a current-mode passive mixer, and a combination of continuous and discrete-time baseband filter with built-in anti-aliasing. The proposed RFVGA achieves high dynamic-range and gain-insensitive input impedance matching performance. The current-mode passive mixer achieves high gain, low noise, and high linearity with low power supplies. A wideband common-gate LNA is presented that overcomes the fundamental trade-off between power and noise match without compromising its stability. The proposed architecture can achieve the minimum noise figure over the previously reported feedback amplifiers in common-gate configuration. The proposed architecture achieves broadband impedance matching, low noise, large gain, enhanced linearity, and wide bandwidth concurrently by employing an efficient and reliable dual negative-feedback. For the wideband Inductorless Balun-LNA, active single-to-differential architecture has been proposed without using any passive inductor on-chip which occupies a lot of silicon area. The proposed Balun-LNA features lower power, wider bandwidth, and better gain and phase balance than previously reported architectures of the same kind. A surface acoustic wave (SAW)-less direct conversion receiver targeted for multistandard applications is proposed and fabricated with TSMC 0.13?m complementary metal-oxide-semiconductor (CMOS) technology. The target is to design a wideband SAW-less direct coversion receiver with a single low noise transconductor and current-mode passive mixer with trans-impedance amplifier utilizing feed-forward compensation. The innovations in the circuit and architecture improves the receiver dynamic range enabling highly linear direct-conversion CMOS front-end for a multi-standard receiver

High efficiency wide-band line drivers in low voltage CMOS using Class-D techniques

In this thesis, the applicability of Class-D amplifiers to integrated wide-band communication line driver applications is studied. While Class-D techniques can address some of the efficiency limitations of linear amplifier structures and have shown promising results in low frequency applications, the low frequency techniques and knowledge need further development in order to improve their practicality for wide band systems. New structures and techniques to extend the application of Class-D to wide-band communication systems, in particular the HomePlug AV wire- line communication standard, will be proposed. Additionally, the digital processing requirements of these wide-band systems drives rapid movement towards nanometer technology nodes and presents new challenges which will be addressed, and new opportunities which will be exploited, for wide-band integrated Class-D line drivers. There are three main contributions of this research. First, a model of Class-D efficiency degradation mechanisms is created, which allows the impact of high-level design choices such as supply voltage, process technology and operating frequency to be assessed. The outcome of this section is a strategy for pushing the high efficiency of Class-D to wide band communication applications, with switching frequencies up to many hundreds of Megahertz. A second part of this research considers the design of efficient, fast and high power Class-D output stages, as these are the major efficiency and bandwidth bottleneck in wide-band applications. A novel NMOS-only totem pole output stage with a fast, integrated drive structure will be proposed. In a third section, a complete wide-band Class-D line driver is designed in a 0.13μm digital CMOS process. The line driver is systematically designed using a rigorous development methodology and the aims are to maximise the achievable signal bandwidth while minimising power dissipation. Novel circuits and circuit structures are proposed as part of this section and the resulting fabricated Class-D line driver test chip shows an efficiency of 15% while driving a 30MHz wide signal with an MTPR of 22dB, at 33mW injected power

Analogue filter networks: developments in theory, design and analyses

Not availabl

Digitally-assisted, ultra-low power circuits and systems for medical applications

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2010.Cataloged from PDF version of thesis.Includes bibliographical references (p. 219-225).In recent years, trends in the medical industry have created a growing demand for a variety of implantable medical devices. At the same time, advances in integrated circuits techniques, particularly in CMOS, have opened possibilities for advanced implantable systems that are very small and consume minimal energy. Minimizing the volume of medical implants is important as it allows for less invasive procedures and greater comfort to patients. Minimizing energy consumption is imperative as batteries must last at least a decade without replacement. Two primary functions that consume energy in medical implants are sensor interfaces that collect information from biomedical signals, and radios that allow the implant to communicate with a base-station outside of the body. The general focus of this work was the development of circuits and systems that minimize the size and energy required to carry out these two functions. The first part of this work focuses on laying down the theoretical framework for an ultra-low power radio, including advances to the literature in the area of super-regeneration. The second part includes the design of a transceiver optimized for medical implants, and its implementation in a CMOS process. The final part describes the design of a sensor interface that leverages novel analog and digital techniques to reduce the system's size and improve its functionality. This final part was developed in conjunction with Marcus Yip.by Jose L. Bohorquez.Ph.D

Magnetometric techniques for the measurement of initial susceptibility and for non-contact sensing of displacement

PhD ThesisPart 1 of the thesis describes a new instrument that simultaneously measures the real magnetic susceptibility X' and the imaginary magnetic susceptibility X". The instrument measures the temperature dependences of X' and X" in rock samples between 16°C and 800°C; natural developments are working down to -200°C and measuring the anisotropy of susceptibility. The instrument's heart is a tuned circuit driven at its natural frequency by a 5MHz crystal oscillator. The tuned circuit's inductance is a sample coil that encloses-a furnace. The random noise level in the signal for X' is 7.4 x l0-13 m3 r. m. s., the noise level in the signal for X" is 2x 10 ^12 m3 r. m. s. Sample volumes are 0.1 cm3 or less. Equations describing the instrument are derived and verified, particular attention is paid to the sample coil. Circuit diagrams are included. Some results are presented and equations that broadly describe the observed temperature dependences of X' and X" are developed. Some methods for substantially improving the instrument's performance are outlined. Part 2 of the thesis describes a new method for non-contact sensing of displacement. A magnet is mounted on the object whose displacement is to be measured. The magnet's field is sensed and fed to a 6502 microprocessor programmed to display the distance between the magnet and the sensor; intervening barriers with a permeability very close to unity do not affect the readings. The accuracy is better than 2.0% of full scale deflection (FSD) over the useful range of 250 mm and better than 0.1% FSD over a range of 110 mm. The magnet's volume is 4.00 mm3 and the moment is 3.1 x 10-7 Vbm. Circuit diagrams are presented and a complete software listing is included, the design will work with any magnet and magnetometer. There are directions for greatly improving the instrument's performance.Natural Environment Research Council

SiGe receiver front ends and flip-chip integrated wideband antennas for millimeter-wave passive imaging

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2009.Includes bibliographical references (p. 177-186).SiGe wideband 77-GHz and 94-GHz front end receivers with integrated antennas for passive imaging have been designed and characterized. These front end systems exhibit wideband performance with the highest gain and lowest noise figures reported thus far for silicon-based systems in the 77-GHz and 94-GHz frequency regimes, to the best of the author's knowledge. These systems each comprise a fully differential integrated antenna, LNA, and a double-balanced mixer. A separate 77-GHz front end also features an on-chip 72-GHz cross-coupled VCO. The 77-GHz front end receiver achieves 46 dB max conversion gain, 6.5-10 dB noise figure (NF), output-referred 1dB compression point of +2 dBm and DC power dissipation (PDc) of 122 mW. The 94-GHz receiver achieves 47 dB max conversion gain, 7-12.5 dB NF, and PDC of 120 mW. The antenna performance yields gains of 10-13 dB over 70-100 GHz, with greater than 90% efficiency. The integrated antenna exhibits a typical loss of 0.5-1 dB, or 80-90% efficiency, and a worst-case radiation loss of _ -2 dB (efficiency = 63%). These reported results exceed published on-chip antenna performance, which typically achieve 10 dB gain from 40-100 GHz.by Johnna Dawn Powell.Ph.D

Conference on Charge-Coupled Device Technology and Applications

Papers were presented from the conference on charge coupled device technology and applications. The following topics were investigated: data processing; infrared; devices and testing; electron-in, x-ray, radiation; and applications. The emphasis was on the advances of mutual relevance and potential significance both to industry and NASA's current and future requirements in all fields of imaging, signal processing and memory

Solid State Circuits Technologies

The evolution of solid-state circuit technology has a long history within a relatively short period of time. This technology has lead to the modern information society that connects us and tools, a large market, and many types of products and applications. The solid-state circuit technology continuously evolves via breakthroughs and improvements every year. This book is devoted to review and present novel approaches for some of the main issues involved in this exciting and vigorous technology. The book is composed of 22 chapters, written by authors coming from 30 different institutions located in 12 different countries throughout the Americas, Asia and Europe. Thus, reflecting the wide international contribution to the book. The broad range of subjects presented in the book offers a general overview of the main issues in modern solid-state circuit technology. Furthermore, the book offers an in depth analysis on specific subjects for specialists. We believe the book is of great scientific and educational value for many readers. I am profoundly indebted to the support provided by all of those involved in the work. First and foremost I would like to acknowledge and thank the authors who worked hard and generously agreed to share their results and knowledge. Second I would like to express my gratitude to the Intech team that invited me to edit the book and give me their full support and a fruitful experience while working together to combine this book