Utilizing Unconventional CMOS Techniques for Low Voltage Low Power Analog Circuits Design for Biomedical Applications

Tato disertační práce se zabývá navržením nízkonapěťových, nízkopříkonových analogových obvodů, které používají nekonvenční techniky CMOS. Lékařská zařízení na bateriové napájení, jako systémy pro dlouhodobý fyziologický monitoring, přenosné systémy, implantovatelné systémy a systémy vhodné na nošení, musí být male a lehké. Kromě toho je nutné, aby byly tyto systémy vybaveny baterií s dlouhou životností. Z tohoto důvodu převládají v biomedicínských aplikacích tohoto typu nízkopříkonové integrované obvody. Nekonvenční techniky jako např. využití transistorů s řízeným substrátem (Bulk-Driven “BD”), s plovoucím hradlem (Floating-Gate “FG”), s kvazi plovoucím hradlem (Quasi-Floating-Gate “QFG”), s řízeným substrátem s plovoucím hradlem (Bulk-Driven Floating-Gate “BD-FG”) a s řízeným substrátem s kvazi plovoucím hradlem (Bulk-Driven Quasi-Floating-Gate “BD-QFG”), se v nedávné době ukázaly jako efektivní prostředek ke zjednodušení obvodového zapojení a ke snížení velikosti napájecího napětí směrem k prahovému napětí u tranzistorů MOS (MOST). V práci jsou podrobně představeny nejdůležitější charakteristiky nekonvenčních technik CMOS. Tyto techniky byly použity pro vytvoření nízko napěťových a nízko výkonových CMOS struktur u některých aktivních prvků, např. Operational Transconductance Amplifier (OTA) založené na BD, FG, QFG, a BD-QFG techniky; Tunable Transconductor založený na BD MOST; Current Conveyor Transconductance Amplifier (CCTA) založený na BD-QFG MOST; Z Copy-Current Controlled-Current Differencing Buffered Amplifier (ZC-CC-CDBA) založený na BD MOST; Winner Take All (WTA) and Loser Take All (LTA) založený na BD MOST; Fully Balanced Four-Terminal Floating Nullor (FBFTFN) založený na BD-QFG technice. Za účelem ověření funkčnosti výše zmíněných struktur, byly tyto struktury použity v několika aplikacích. Výkon navržených aktivních prvků a příkladech aplikací je ověřován prostřednictvím simulačních programů PSpice či Cadence za použití technologie 0.18 m CMOS.This doctoral thesis deals with designing ultra-low-voltage (LV) low-power (LP) analog circuits utilizing the unconventional CMOS techniques. Battery powered medical devices such as; long term physiological monitoring, portable, implantable, and wearable systems need to be small and lightweight. Besides, long life battery is essential need for these devices. Thus, low-power integrated circuits are always paramount in such biomedical applications. Recently, unconventional CMOS techniques i.e. Bulk-Driven (BD), Floating-Gate (FG), Quasi-Floating-Gate (QFG), Bulk-Driven Floating-Gate (BD-FG) and Bulk-Driven Quasi-Floating-Gate (BD-QFG) MOS transistors (MOSTs) have revealed as effective devices to reduce the circuit complexity and push the voltage supply of the circuit towards threshold voltage of the MOST. In this work, the most important features of the unconventional CMOS techniques are discussed in details. These techniques have been utilized to perform ultra-LV LP CMOS structures of several active elements i.e. Operational Transconductance Amplifier (OTA) based on BD, FG, QFG, and BD-QFG techniques; Tunable Transconductor based on BD MOST; Current Conveyor Transconductance Amplifier (CCTA) based on BD-QFG MOST; Z Copy-Current Controlled-Current Differencing Buffered Amplifier (ZC-CC-CDBA) based on BD MOST; Winner Take All (WTA) and Loser Take All (LTA) based on BD MOST; Fully Balanced Four-Terminal Floating Nullor (FBFTFN) based on BD-QFG technique. Moreover, to verify the workability of the proposed structures, they were employed in several applications. The performance of the proposed active elements and their applications were investigated through PSpice or Cadence simulation program using 0.18 m CMOS technology.

360 nW gate-driven ultra-low voltage CMOS linear transconductor with 1 MHz bandwidth and wide input range

A low voltage linear transconductor is introduced. The circuit is a pseudo differential architecture that operates with ±0.2V supplies and uses 900nA total biasing current. It employs a floating battery technique to achieve low voltage operation. The transconductor has a 1MHz bandwidth. It exhibits a SNR = 72dB, SFDR = 42dB and THD = 0.83% for a 100mVpp 10kHz sinusoidal input signal. Moreover, stability is not affected by the capacitance of the signal source. The circuit has been validated with a prototype chip fabricated in a 130nm CMOS technology.This work was supported in part by the Agencia Estatal de Investigacion/Fondo Europeo de Desarrollo Regional under Grant TEC2016-80396-C2. The work of Hector D. Rico-Aniles was supported by the Mexican Consejo Nacional de Ciencia y Tecnologia for the through an Academic Scholarship under Grant 408946

Circuits for Analog Signal Processing Employing Unconventional Active Elements

Disertační práce se zabývá zaváděním nových struktur moderních aktivních prvků pracujících v napěťovém, proudovém a smíšeném režimu. Funkčnost a chování těchto prvků byly ověřeny prostřednictvím SPICE simulací. V této práci je zahrnuta řada simulací, které dokazují přesnost a dobré vlastnosti těchto prvků, přičemž velký důraz byl kladen na to, aby tyto prvky byly schopny pracovat při nízkém napájecím napětí, jelikož poptávka po přenosných elektronických zařízeních a implantabilních zdravotnických přístrojích stále roste. Tyto přístroje jsou napájeny bateriemi a k tomu, aby byla prodloužena jejich životnost, trend navrhování analogových obvodů směřuje k stále většímu snižování spotřeby a napájecího napětí. Hlavním přínosem této práce je návrh nových CMOS struktur: CCII (Current Conveyor Second Generation) na základě BD (Bulk Driven), FG (Floating Gate) a QFG (Quasi Floating Gate); DVCC (Differential Voltage Current Conveyor) na základě FG, transkonduktor na základě nové techniky BD_QFG (Bulk Driven_Quasi Floating Gate), CCCDBA (Current Controlled Current Differencing Buffered Amplifier) na základě GD (Gate Driven), VDBA (Voltage Differencing Buffered Amplifier) na základě GD a DBeTA (Differential_Input Buffered and External Transconductance Amplifier) na základě BD. Dále je uvedeno několik zajímavých aplikací užívajících výše jmenované prvky. Získané výsledky simulací odpovídají teoretickým předpokladům.The dissertation thesis deals with implementing new structures of modern active elements working in voltage_, current_, and mixed mode. The functionality and behavior of these elements have been verified by SPICE simulation. Sufficient numbers of simulated plots are included in this thesis to illustrate the precise and strong behavior of those elements. However, a big attention to implement active elements by utilizing LV LP (Low Voltage Low Power) techniques is given in this thesis. This attention came from the fact that growing demand of portable electronic equipments and implantable medical devices are pushing the development towards LV LP integrated circuits because of their influence on batteries lifetime. More specifically, the main contribution of this thesis is to implement new CMOS structures of: CCII (Current Conveyor Second Generation) based on BD (Bulk Driven), FG (Floating Gate) and QFG (Quasi Floating Gate); DVCC (Differential Voltage Current Conveyor) based on FG; Transconductor based on new technique of BD_QFG (Bulk Driven_Quasi Floating Gate); CCCDBA (Current Controlled Current Differencing Buffered Amplifier) based on conventional GD (Gate Driven); VDBA (Voltage Differencing Buffered Amplifier) based on GD. Moreover, defining new active element i.e. DBeTA (Differential_Input Buffered and External Transconductance Amplifier) based on BD is also one of the main contributions of this thesis. To confirm the workability and attractive properties of the proposed circuits many applications were exhibited. The given results agree well with the theoretical anticipation.

A wide dynamic range high-q high-frequency bandpass filter with an automatic quality factor tuning scheme

An 80 MHz bandpass filter with a tunable quality factor of 16∼44 using an improved transconductor circuit is presented. A noise optimized biquad structure for high-Q, high- frequency bandpass filter is proposed. The quality factor of the filter is tuned using a new quality factor locked loop algorithm. It was shown that a second-order quality factor locked loop is necessary and sufficient to tune the quality factor of a bandpass filter with zero steady state error. The accuracy, mismatch, and sensitivty analysis of the new tuning scheme was performed and analyzed. Based on the proposed noise optimized filter structure and new quality factor tuning scheme, a biquad filter was designed and fabricated in 0.25 μm BiCMOS process. The measured results show that the biquad filter achieves a SNR of 45 dB at IMD of 40 dB. The P-1dB compression point and IIP3 of the filter are -10 dBm and -2.68 dBm, respectively. The proposed biquad filter and quality factor tuning scheme consumes 58mW and 13 mW of power at 3.3 V supply.Ph.D.Committee Chair: Allen Phillip; Committee Member: Hasler Paul; Committee Member: Keezer David; Committee Member: Kenny James; Committee Member: Pan Ronghu

Analogue micropower FET techniques review

A detailed introduction to published analogue circuit design techniques using Si and Si/SiGe FET devices for very low-power applications is presented in this review. The topics discussed include sub-threshold operation in FET devices, micro-current mirrors and cascode techniques, voltage level-shifting and class-AB operation, the bulk-drive approach, the floating-gate method, micropower transconductance-capacitance and log-domain filters and strained-channel FET technologies

An Analog VLSI Deep Machine Learning Implementation

Machine learning systems provide automated data processing and see a wide range of applications. Direct processing of raw high-dimensional data such as images and video by machine learning systems is impractical both due to prohibitive power consumption and the “curse of dimensionality,” which makes learning tasks exponentially more difficult as dimension increases. Deep machine learning (DML) mimics the hierarchical presentation of information in the human brain to achieve robust automated feature extraction, reducing the dimension of such data. However, the computational complexity of DML systems limits large-scale implementations in standard digital computers. Custom analog signal processing (ASP) can yield much higher energy efficiency than digital signal processing (DSP), presenting means of overcoming these limitations. The purpose of this work is to develop an analog implementation of DML system. First, an analog memory is proposed as an essential component of the learning systems. It uses the charge trapped on the floating gate to store analog value in a non-volatile way. The memory is compatible with standard digital CMOS process and allows random-accessible bi-directional updates without the need for on-chip charge pump or high voltage switch. Second, architecture and circuits are developed to realize an online k-means clustering algorithm in analog signal processing. It achieves automatic recognition of underlying data pattern and online extraction of data statistical parameters. This unsupervised learning system constitutes the computation node in the deep machine learning hierarchy. Third, a 3-layer, 7-node analog deep machine learning engine is designed featuring online unsupervised trainability and non-volatile floating-gate analog storage. It utilizes massively parallel reconfigurable current-mode analog architecture to realize efficient computation. And algorithm-level feedback is leveraged to provide robustness to circuit imperfections in analog signal processing. At a processing speed of 8300 input vectors per second, it achieves 1×1012 operation per second per Watt of peak energy efficiency. In addition, an ultra-low-power tunable bump circuit is presented to provide similarity measures in analog signal processing. It incorporates a novel wide-input-range tunable pseudo-differential transconductor. The circuit demonstrates tunability of bump center, width and height with a power consumption significantly lower than previous works

Power-efficient current-mode analog circuits for highly integrated ultra low power wireless transceivers

In this thesis, current-mode low-voltage and low-power techniques have been applied to implement novel analog circuits for zero-IF receiver backend design, focusing on amplification, filtering and detection stages. The structure of the thesis follows a bottom-up scheme: basic techniques at device level for low voltage low power operation are proposed in the first place, followed by novel circuit topologies at cell level, and finally the achievement of new designs at system level. At device level the main contribution of this work is the employment of Floating-Gate (FG) and Quasi-Floating-Gate (QFG) transistors in order to reduce the power consumption. New current-mode basic topologies are proposed at cell level: current mirrors and current conveyors. Different topologies for low-power or high performance operation are shown, being these circuits the base for the system level designs. At system level, novel current-mode amplification, filtering and detection stages using the former mentioned basic cells are proposed. The presented current-mode filter makes use of companding techniques to achieve high dynamic range and very low power consumption with for a very wide tuning range. The amplification stage avoids gain bandwidth product achieving a constant bandwidth for different gain configurations using a non-linear active feedback network, which also makes possible to tune the bandwidth. Finally, the proposed current zero-crossing detector represents a very power efficient mixed signal detector for phase modulations. All these designs contribute to the design of very low power compact Zero-IF wireless receivers. The proposed circuits have been fabricated using a 0.5μm double-poly n-well CMOS technology, and the corresponding measurement results are provided and analyzed to validate their operation. On top of that, theoretical analysis has been done to fully explore the potential of the resulting circuits and systems in the scenario of low-power low-voltage applications.Programa Oficial de Doctorado en Tecnologías de las Comunicaciones (RD 1393/2007)Komunikazioen Teknologietako Doktoretza Programa Ofiziala (ED 1393/2007

Advances in Solid State Circuit Technologies

This book brings together contributions from experts in the fields to describe the current status of important topics in solid-state circuit technologies. It consists of 20 chapters which are grouped under the following categories: general information, circuits and devices, materials, and characterization techniques. These chapters have been written by renowned experts in the respective fields making this book valuable to the integrated circuits and materials science communities. It is intended for a diverse readership including electrical engineers and material scientists in the industry and academic institutions. Readers will be able to familiarize themselves with the latest technologies in the various fields