Design of low–power 4-bit Flash ADC using Multiplexer based encoder in 90nm CMOS process

This work describes a 4-bit Flash ADC with low power consumption. The performance metrics of a Flash ADC depend on the kind of comparator and encoder used. Hence open-loop comparator and mux-based encoder are used to obtain improved performance. Simulation results shows that the simulated  design consumes 0.265mW of power in 90nm CMOS technology using cadence-virtuoso software. The circuit operates with an operating frequency of 100MHz  and  supply  voltage of 1V

Design of low–power 4-bit Flash ADC using Multiplexer based encoder in 90nm CMOS process

This work describes a 4-bit Flash ADC with low power consumption. The performance metrics of a Flash ADC depend on the kind of comparator and encoder used. Hence open-loop comparator and mux-based encoder are used to obtain improved performance. Simulation results shows that the simulated  design consumes 0.265mW of power in 90nm CMOS technology using cadence-virtuoso software. The circuit operates with an operating frequency of 100MHz  and  supply  voltage of 1V

Design of Energy-Efficient A/D Converters with Partial Embedded Equalization for High-Speed Wireline Receiver Applications

As the data rates of wireline communication links increases, channel impairments such as skin effect, dielectric loss, fiber dispersion, reflections and cross-talk become more pronounced. This warrants more interest in analog-to-digital converter (ADC)-based serial link receivers, as they allow for more complex and flexible back-end digital signal processing (DSP) relative to binary or mixed-signal receivers. Utilizing this back-end DSP allows for complex digital equalization and more bandwidth-efficient modulation schemes, while also displaying reduced process/voltage/temperature (PVT) sensitivity. Furthermore, these architectures offer straightforward design translation and can directly leverage the area and power scaling offered by new CMOS technology nodes. However, the power consumption of the ADC front-end and subsequent digital signal processing is a major issue. Embedding partial equalization inside the front-end ADC can potentially result in lowering the complexity of back-end DSP and/or decreasing the ADC resolution requirement, which results in a more energy-effcient receiver. This dissertation presents efficient implementations for multi-GS/s time-interleaved ADCs with partial embedded equalization. First prototype details a 6b 1.6GS/s ADC with a novel embedded redundant-cycle 1-tap DFE structure in 90nm CMOS. The other two prototypes explain more complex 6b 10GS/s ADCs with efficiently embedded feed-forward equalization (FFE) and decision feedback equalization (DFE) in 65nm CMOS. Leveraging a time-interleaved successive approximation ADC architecture, new structures for embedded DFE and FFE are proposed with low power/area overhead. Measurement results over FR4 channels verify the effectiveness of proposed embedded equalization schemes. The comparison of fabricated prototypes against state-of-the-art general-purpose ADCs at similar speed/resolution range shows comparable performances, while the proposed architectures include embedded equalization as well

A 0.2pJ/conversion-step 6-bit 200MHz flash ADC with redundancy

Comunicación presentada al "27th Conference on Design of Circuits and Integrated Systems (DCIS 2012)" celebrada del 28 al 30 de Noviembre del 2012 en Avignon (Francia), organizada por el LIRMM laboratory of Montpellier: http://www.lirmm.fr/dcis2012/index.phpIn this paper, a 200MHz 6-bit Flash analog-to-digital converter (ADC) is presented. The principal objective is to obtain a digital-friendly converter. Hence, small and simple latched comparators are used and redundancy allows reducing the offset down to an acceptable level. This obviously requires calibration but reduces power consumption, since small size transistors can be used and the unused comparators are powered down. The proposed ADC is designed in UMC 0:18m CMOS technology. Full electrical simulations show that the ADC reaches an effective number of bits (ENOB) of 5.3 associated to a signal-to-noise-anddistortion ratio (SNDR) is 33dB. The converter consumes only 1.56mW and has figure-of-merit (FoM) of 0.2 pJ / conversion step.This work has been partially funded by the Junta de Andalucia project P09-TIC-5386, the Ministerio de Economia y Competitividad project TEC2011-28302, both of them cofinanced by the FEDER program.Peer Reviewe

Carbon footprint of 3D-printed bone tissue engineering scaffolds: an life cycle assessment study

The bone tissue engineering scaffolds is one of the methods for repairing bone defects caused by various factors. According to modern tissue engineering technology, three-dimensional (3D) printing technology for bone tissue engineering provides a temporary basis for the creation of biological replacements. Through the generated 3D bone tissue engineering scaffolds from previous studies, the assessment to evaluate the environmental impact has shown less attention in research. Therefore, this paper is aimed to propose the Model of life cycle assessment (LCA) for 3D bone tissue engineering scaffolds of 3D gel-printing technology and presented the analysis technique of LCA from cradle-to-gate for assessing the environmental impacts of carbon footprint. Acrylamide (C3H5NO), citric acid (C6H8O7), N,N-Dimethylaminopropyl acrylamide (C8H16N2O), deionized water (H2O), and 2-Hydroxyethyl acrylate (C5H8O3) was selected as the material resources. Meanwhile, the 3D gel-printing technology was used as the manufacturing processes in the system boundary. The analysis is based on the LCA Model through the application of GaBi software. The environmental impact was assessed in the 3D gel-printing technology and it was obtained that the system shows the environmental impact of global warming potential (GWP). All of the emissions contributed to GWP have been identified such as emissions to air, freshwater, seawater, and industrial soil. The aggregation of GWP result in the stage of manufacturing process for input and output data contributed 47.6% and 32.5% respectively. Hence, the data analysis of the results is expected to use for improving the performance at the material and manufacturing process of the product life cycle

A Low Power Comparator Design for 6-Bit Flash ADC in 90-Nm CMOS

ABSTRACT: The main focus of this paper is to design a "Low power Flash ADC" for ultra-wide band applications using CMOS 90nm technology. Flash ADC consists of a reference generator, array of comparators, 1-out-of N code generator, Fat tree encoder and output D latches. The demanding issues in the design of a low power flash ADC is the design of low power latched comparator. The proposed comparator in this paper is designed using 90nm technology at 0.8V DC voltage source using H SPICE tool. The Simulation results of a 6-bit flash ADC is shown for a sampling frequency up to 1.2GHz showing an average power dissipation of 7.67mW. KEYWORDS: Flash ADC, Preamplifier based latch Comparator, Low power consumption. I.INTRODUCTION Analog to digital converters plays a prominent role to interact with the real world. Flash ADC is the fastest ADC in comparison with other ADC architectures. Flash ADC is the best choice in high speed low resolution applications. It is highly used in high data rate links, high speed instrumentation, radar, digital oscilloscopes and optical communications. Since flash ADC is operating in parallel conversion method, maximum operating frequency in the range of gigahertz is possible. In this paper we are designing a low power, high speed comparator. Here we are combining two recently published research papers to achieve the low power and high speed in ADC. In [2] a Low power flash ADC with 6 bit resolution uses inverter based comparator which consumes a less power of 300 μW at a sampling rate of 50MS/s. In [3] a high speed flash ADC with 6 bit resolution uses differential clocked comparator architecture. Even though the sampling speed is 1GS/s, the comparator block alone consumes 2mW of power. The present work collaborates the above explained two papers in order to fill the gap by proposing a 6 bit flash ADC for high speed applications (up to 5 GS/s) and slightly higher power compared to the inverter based ADC. The proposed ADC employs a modified version of the comparator block presented in [3] to achieve low power and high speed of operation. II.LITERATURE SURVEY R Komar, et.al, proposed "A 0.5V 300μw 50MS/s 180nm 6-bit flash adc using inverter based comparators". This paper presents a 0.5 V, 50 MS/s, 6 bit Flash ADC designed using 180 nm CMOS technology. To reduce the silicon area and power requirement, an inverter based comparator is used in the design. Low threshold MOSFETs are used for the ultra low voltage operation. A simple clock delaying technique and back to back inverters in the comparator have been used to increase the power efficiency and speed of operation. A fat tree encoder design is used for digitizing comparator outputs. The measured SNDR at input frequency of 5.1 MHz is 31 dB. The measured maximum INL and DNL for a ramp input are 0.375 LSB and 0.025 LSB, respectively. The design consumes a very low power of 0.3mW. S. Sheikhaei, et.al, proposed "A 0.35 μm cmos comparator circuit for high-speed adc applications". A high-speed differential clocked comparator circuit is presented. The comparator consists of a preamplifier and a latch stage followed by a dynamic latch that operates as an output sampler. The output sampler circuit consists of a full transmission gate (TG) and two inverters. The use of this sampling stage results in a reduction in the power consumption of this high-speed comparator. Simulations show that charge injection of the TG adds constructively to the sampled signal value, therefore amplifying the sampled signal with a modest gain of 1.15. Combined with the hig