A Survey of Non-conventional Techniques for Low-voltage Low-power Analog Circuit Design

Designing integrated circuits able to work under low-voltage (LV) low-power (LP) condition is currently undergoing a very considerable boom. Reducing voltage supply and power consumption of integrated circuits is crucial factor since in general it ensures the device reliability, prevents overheating of the circuits and in particular prolongs the operation period for battery powered devices. Recently, non-conventional techniques i.e. bulk-driven (BD), floating-gate (FG) and quasi-floating-gate (QFG) techniques have been proposed as powerful ways to reduce the design complexity and push the voltage supply towards threshold voltage of the MOS transistors (MOST). Therefore, this paper presents the operation principle, the advantages and disadvantages of each of these techniques, enabling circuit designers to choose the proper design technique based on application requirements. As an example of application three operational transconductance amplifiers (OTA) base on these non-conventional techniques are presented, the voltage supply is only ±0.4 V and the power consumption is 23.5 µW. PSpice simulation results using the 0.18 µm CMOS technology from TSMC are included to verify the design functionality and correspondence with theory

Performance enhancement in the desing of amplifier and amplifier-less circuits in modern CMOS technologies.

In the context of nowadays CMOS technology downscaling and the increasing demand of high performance electronics by industry and consumers, analog design has become a major challenge. On the one hand, beyond others, amplifiers have traditionally been a key cell for many analog systems whose overall performance strongly depends on those of the amplifier. Consequently, still today, achieving high performance amplifiers is essential. On the other hand, due to the increasing difficulty in achieving high performance amplifiers in downscaled modern technologies, a different research line that replaces the amplifier by other more easily achievable cells appears: the so called amplifier-less techniques. This thesis explores and contributes to both philosophies. Specifically, a lowvoltage differential input pair is proposed, with which three multistage amplifiers in the state of art are designed, analysed and tested. Moreover, a structure for the implementation of differential switched capacitor circuits, specially suitable for comparator-based circuits, that features lower distortion and less noise than the classical differential structures is proposed, an, as a proof of concept, implemented in a ΔΣ modulator

±0.3V Bulk-Driven Fully Differential Buffer with High Figures of Merit

A high performance bulk-driven rail-to-rail fully differential buffer operating from ±0.3V supplies in 180 nm CMOS technology is reported. It has a differential–difference input stage and common mode feedback circuits implemented with no-tail, high CMRR bulk-driven pseudo-differential cells. It operates in subthreshold, has infinite input impedance, low output impedance (1.4 kΩ), 86.77 dB DC open-loop gain, 172.91 kHz bandwidth and 0.684 μW static power dissipation with a 50-pF load capacitance. The buffer has power efficient class AB operation, a small signal figure of merit FOMSS = 12.69 MHzpFμW−1, a large signal figure of merit FOMLS = 34.89 (V/μs) pFμW−1, CMRR = 102 dB, PSRR+ = 109 dB, PSRR− = 100 dB, 1.1 μV/√Hz input noise spectral density, 0.3 mVrms input noise and 3.5 mV input DC offset voltage.Junta de Andalucía - Consejería de Economía, Conocimiento, Empresas y Universidades P18-FR-4317Agencia Estatal de Investigación - FEDER PID2019-107258RB-C3

An improved reversed miller compensation technique for three-stage CMOS OTAs with double pole-zero cancellation and almost single-pole frequency response

This paper presents an improved reversed nested Miller compensation technique exploiting a single additional feed-forward stage to obtain double pole-zero cancellation and ideally single-pole behavior, in a three-stage Miller amplifier. The approach allows designing a three-stage operational transconductance amplifier (OTA) with one dominant pole and two (ideally) mutually cancelling pole-zero doublets. We demonstrate the robustness of the proposed cancellation technique, showing that it is not significantly influenced by process and temperature variations. The proposed design equations allow setting the unity-gain frequency of the amplifier and the complex poles' resonance frequency and quality factor. We introduce the notion of bandwidth efficiency to quantify the OTA performance with respect to a telescopic cascode OTA for given load capacitance and power consumption constraints and demonstrate analytically that the proposed approach allows a bandwidth efficiency that can ideally approach 100%. A CMOS implementation of the proposed compensation technique is provided, in which a current reuse scheme is used to reduce the total current consumption. The OTA has been designed using a 130-nm CMOS process by STMicroelectronics and achieves a DC gain larger than 120 dB, with almost single-pole frequency response. Monte Carlo simulations have been performed to show the robustness of the proposed approach to process, voltage, and temperature (PVT) variations and mismatches

Review on Design of OTA Using Non-Conventional Analog Techniques

The OTA is an amplifier whose differential input voltage produces an output current. Thus, it is a voltage controlled current source. Operational transconductance amplifier is one of the most significant building-blocks in integrated continuous-time filters. A review of various non-conventional analog design techniques has been done in this paper. Several previous works have been studied and their comparison on various performance parameters is shown. This paper starts with the introduction of OTA, followed by the discussion on various OTA design techniques along with their block diagram in addition to advantages and disadvantages of these techniques. Two comparative tables are shown at the end

A 0.3 V rail-to-rail ultra-low-power OTA with improved bandwidth and slew rate

In this paper, we present a novel operational transconductance amplifier (OTA) topology based on a dual-path body-driven input stage that exploits a body-driven current mirror-active load and targets ultra-low-power (ULP) and ultra-low-voltage (ULV) applications, such as IoT or biomedical devices. The proposed OTA exhibits only one high-impedance node, and can therefore be compensated at the output stage, thus not requiring Miller compensation. The input stage ensures rail-to-rail input common-mode range, whereas the gate-driven output stage ensures both a high open-loop gain and an enhanced slew rate. The proposed amplifier was designed in an STMicroelectronics 130 nm CMOS process with a nominal supply voltage of only 0.3 V, and it achieved very good values for both the small-signal and large-signal Figures of Merit. Extensive PVT (process, supply voltage, and temperature) and mismatch simulations are reported to prove the robustness of the proposed amplifier

Design of a Reference Buffer for a Delta-Sigma ADC with Current DAC

In analog to digital conversion, it’s necessary to provide a reference voltage to the Analog to Digital Converter (ADC), in order to quantify the input signal. However, as the ADC has a switch constantly commuting on its input it will cause perturbations on the reference voltage provided by the Bandgap circuit. Thus, it will interfere with the normal behaviour of the Bandgap circuit, which will longer be capable of provide the desired reference voltage. Besides, if the reference voltage is not constant in the desired value the output code generated by the ADC will have errors. In order to avoid conversion errors it will be needed to introduce a buffer between the Bandgap and the ADC. Thus, taking advantage from the characteristics of the buffer (low output impedance, high input impedance and unitary gain) the system will be capable of recover from the perturbations introduced by the ADC in the reference voltage. Therefore, in this thesis are studied some of the already existing architectures of buffers, in order to see the advantages and disadvantages of each one. This way were chosen the best three architectures from a theoretical point of view, to implement and simulate, to obtain all the needed information in order to better compare them

Low-Voltage Bulk-Driven Amplifier Design and Its Application in Implantable Biomedical Sensors

The powering unit usually represents a significant component of the implantable biomedical sensor system since the integrated circuits (ICs) inside for monitoring different physiological functions consume a great amount of power. One method to reduce the volume of the powering unit is to minimize the power supply voltage of the entire system. On the other hand, with the development of the deep sub-micron CMOS technologies, the minimum channel length for a single transistor has been scaled down aggressively which facilitates the reduction of the chip area as well. Unfortunately, as an inevitable part of analytic systems, analog circuits such as the potentiostat are not amenable to either low-voltage operations or short channel transistor scheme. To date, several proposed low-voltage design techniques have not been adopted by mainstream analog circuits for reasons such as insufficient transconductance, limited dynamic range, etc. Operational amplifiers (OpAmps) are the most fundamental circuit blocks among all analog circuits. They are also employed extensively inside the implantable biosensor systems. This work first aims to develop a general purpose high performance low-voltage low-power OpAmp. The proposed OpAmp adopts the bulk-driven low-voltage design technique. An innovative low-voltage bulk-driven amplifier with enhanced effective transconductance is developed in an n-well digital CMOS process operating under 1-V power supply. The proposed circuit employs auxiliary bulk-driven input differential pairs to achieve the input transconductance comparable with the traditional gate-driven amplifiers, without consuming a large amount of current. The prototype measurement results show significant improvements in the open loop gain (AO) and the unity-gain bandwidth (UGBW) compared to other works. A 1-V potentiostat circuit for an implantable electrochemical sensor is then proposed by employing this bulk-driven amplifier. To the best of the author’s knowledge, this circuit represents the first reported low-voltage potentiostat system. This 1-V potentiostat possesses high linearity which is comparable or even better than the conventional potentiostat designs thanks to this transconductance enhanced bulk-driven amplifier. The current consumption of the overall potentiostat is maintained around 22 microampere. The area for the core layout of the integrated circuit chip is 0.13 mm2 for a 0.35 micrometer process